Narendiran S

Sahoo S.K.

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Energy Procedia

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.

IEEE Access

Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

Design and Analysis Three Phase Three Level Diode-Clamped Grid Connected Inverter

IET Power Electronics

Hybrid topology of symmetrical multilevel inverter using less number of devices

Novel carrier-based hybrid pulse width modulation method for cascaded capacitor-clamp multilevel inverter

IEEE Transactions on Industrial Electronics

Level- and Phase-Shifted PWM for Seven-Level Switched-Capacitor Inverter Using Series/Parallel Conversion

Performance evaluation of carrier rotation strategy in level-shifted pulse-width modulation technique

A Single Phase Reduced Device Count Multilevel Inverter Topology Using MCPWM for Renewable Energy Systems

Journal	Data powered by TypesetEnergy Procedia
Publisher	Data powered by TypesetElsevier BV
ISSN	1876-6102
Open Access	Yes