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A survey on multipliers, adders and adiabatic logic styles suitable for power reduction
S. Jagadeesh Babu,
Published in Institute of Physics Publishing
2018
Volume: 1026
   
Issue: 1
Abstract
Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic. © Published under licence by IOP Publishing Ltd.
About the journal
JournalJournal of Physics: Conference Series
PublisherInstitute of Physics Publishing
ISSN17426588