This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.

Sivasankaran K

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Partha Sharathi Mallick

Department of Instrumentation

School of Electrical Engineering

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Journal of Computational Electronics

Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K.

IET Circuits, Devices & Systems

High-speed sub-threshold operation of carbon nanotube interconnects

In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut-off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability. © 2018 John Wiley & Sons, Ltd.

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Impact of high k spacer on RF stability performance of double gate junctionless transistor

In this paper we investigate the impact of process parameter variations such as temperature (T), channel doping concentration (ND), Fin height (Hfin) and Fin width (Wfin) on Radio Frequency (RF) stability performance of 20 nm Silicon on Insulator Junctionless FinFET (SOI JLFinFET). The developed RF stability model provides relation between critical frequency (fk) and small signal parameters which can be optimized for improved stability. Results shows as temperature increases (27–200 °C) cutoff frequency (fT) and maximum oscillation frequency (fmax) reduced by 12% and 8% respectively also stability factor (K) decreases by 20% at high frequency. Increasing ND, Hfin and Wfin increases fT and fmax but degrades stability performance. The result also provides optimized design guideline for operating SOI JLFinFET under RF range. © 2016 Elsevier Ltd

Microelectronics Journal

RF stability performance of SOI junctionless FinFET and impact of process variation

This paper presents the effect of process parameter variation such as oxide material, oxide thickness, doping concentration along with bias conditions and different high-k dielectric on RF stability performance of Junctionless Tri-Gate Transistor (JLTGT). The small signal RF parameter is obtained from extracted device parameters using TCAD (Technology Computer Aided Design). The results show that optimized JLTGT shows good RF stability performance.

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

Impact of bias, doping and High-K dielectric on RF stability performance of junctionless tri-gate transistor

This paper presents the impact of parameter fluctuation due to process variation on radio frequency (RF) stability performance of double gate tunnel FET (DG TFET). The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit (FoM) such as cut-off frequency (ft), maximum oscillation frequency (fmax) along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines of DG TFET for RF applications.

Journal of Semiconductors

Impact of parameter fluctuations on RF stability performance of DG tunnel FET

This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.

Stability performance of optimized symmetric DG-MOSFET

This article presents structure and bias optimization techniques for the radio frequency (RF) stability of silicon nanowire transistor. The RF parameters are extracted using device simulation. The device stability is obtained for various bias conditions and geometry, and observed that the proposed device structure shows good stability response. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2114–2117, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27016

Journal	Data powered by TypesetJournal of Computational Electronics
Publisher	Data powered by TypesetSpringer Science and Business Media LLC
ISSN	1569-8025
Open Access	0