This paper focuses a new modified multi-level DC link inverter with reduced switches. It presents a comparative analysis of the modified inverter with the existing cascaded H-bridge multilevel inverter (CHBMLI) fed with induction motor drive. The modified multilevel dc link inverter (MLDCL) which is proposed greatly minimizes the switch count as well as the number of gate drivers compare to other family of multilevel inverters. PWM technique which has been applied for proposed inverter and CHBMLI is level shifted multi carrier PWM. An exhaustive survey has taken to investigate the performance characteristics such as total harmonic distortion (THD) and efficiency of various levels of inverter. For the meticulous analysis eleven-level DC link inverter and the existing eleven-level CHBMLI are built using MATLAB/SIMULINK platform. The proposed inverter is observed to have a better performance and relatively less cost compared with the conventional scheme. © 2017 The Authors. Published by Elsevier Ltd.

Vijaya Priya P

Department of Electrical Engineering

School of Electrical Engineering

Vellore Campus

Poompavai T

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Energy Procedia

Renewable and Sustainable Energy Reviews

Control and energy management strategies applied for solar photovoltaic and wind energy fed water pumping system: A review

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.

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Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

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Journal	Data powered by TypesetEnergy Procedia
Publisher	Data powered by TypesetElsevier BV
ISSN	1876-6102
Open Access	Yes