A new cascaded multilevel inverter (MLI) is presented with the aim of utilising lesser number of switches, better modularity and reduced voltage stress. The new structure configured under symmetric and asymmetric mode, produces all odd and even voltage levels. This structure comprises semi-half-bridge cells connected in series with crisscross switches to generate any target level for synthesising the sinusoidal output voltage waveform. In extension to the proposed topology, subinverters derived from the proposed MLI are cascaded with an objective to produce more voltage levels with reduced standing voltage. Compared with the cascading H-bridge topology, the proposed MLI and the extended version uses lesser number of semi-conductor switches. The MATLAB R2013b-based simulation results along with the experimental results validate the proposed topology. © The Institution of Engineering and Technology 2017.