In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.

Sivanantham S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Partha Sharathi Mallick

Department of Instrumentation

School of Electrical Engineering

Sarathkumar K

Manuel J.P

Perinbam J.R.P.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

2012 International Symposium on Electronic System Design (ISED)

In this paper, we present a hybrid X-filling and two-stage test&nbsp;<a href="https://www.sciencedirect.com/topics/computer-science/data-compression">data compression</a>&nbsp;(TS-TDC) techniques for digital&nbsp;<a href="https://www.sciencedirect.com/topics/engineering/vlsi-circuits">VLSI circuits</a>&nbsp;to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based&nbsp;<a href="https://www.sciencedirect.com/topics/computer-science/huffman-coding">Huffman Coding</a>&nbsp;(RLHC) since ASRL&nbsp;<a href="https://www.sciencedirect.com/topics/engineering/codewords">codewords</a>&nbsp;contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76%&nbsp;<a href="https://www.sciencedirect.com/topics/engineering/compression-ratio">compression ratio</a>&nbsp;for ISCAS’89 benchmark circuits.

Computers & Electrical Engineering

Two-stage low power test data compression for digital VLSI circuits

The ever-increasing test data volume and test power consumption are the two major issues in testing of digital integrated circuits. This paper presents an efficient technique to reduce test data volume and test power simultaneously. The pre-generated test sets are divided into two groups based on the number of unspecified bits in each test set. Test compression procedure is applied only to the group of test sets which contain more unspecified bits and the power reduction technique is applied to the remaining test sets. In the proposed approach, the unspecified bits in the pre-generated test sets are selectively mapped with 0s or 1s based on their effectiveness in reducing the test data volume and power consumptions. We also present a simple decoder architecture for on-chip decompression. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed technique compared with other test-independent compression techniques.

Fulltext

Low-power selective pattern compression for scan-based test applications

Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power. © 2013 IEEE.

2013 International Conference on Information Communication and Embedded Systems (ICICES)

Adaptive Low Power RTPG for BIST based test applications

This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used. © 2013 IEEE.

2013 International Conference on Computer Communication and Informatics

Adaptive test clock scheme for low transition LFSR and external scan based testing

This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the pattern. After filling the X-bits for shift power reduction, the patterns are compressed based on shifted alternating frequency directed run-length coding, which is suitable for encoding pre-computed test set of embedded cores in System-on-Chip(SoC). The experimental results on ISCAS'89 benchmark circuits show that our scheme provides better compression efficiency as well as significant reduction in test power.

2012 International Conference on Advances in Computing and Communications

Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies

Reduction of testing power with pulsed scan flip-flop for scan based testing

This paper proposes a novel approach for reducing the shifting and capture power by a fan-out aware modified adjacent X-filling technique. This approach reduces the time complexity and number of iterations in addition to the reduction of test power. Experimental results obtained from ISCAS'89 circuits are compared with existing techniques prove that the proposed ATPG methodology is suitable to test the scan based system-on-chip architecture with reduced testing power.

Journal	Data powered by Typeset2012 International Symposium on Electronic System Design (ISED)
Publisher	Data powered by TypesetIEEE
Open Access	0