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Design and implementation of low power high stability 8T SRAM
R. Harshni,
Published in IOP Publishing Ltd
Volume: 1716
Issue: 1
This paper examines about the power decrease system in a memory cell. It affords a low power high stability i8T Static Random Access Memory (SRAM) cell. Two typically used SRAM cells are analyzed in phrases of their stability and power. It presents improved performance as analyzed with traditional 6T SRAM cell in iterms iof leakage power and static noise margin. The scheme of ilow power i8T SRAM is executed along enforcing power gating approach. Power gating is executed with the aid of putting ia itransistor iin ibetween the i8T SRAM cell and VDD ior iground. However, this avoids ithe idirect VDD and ground path and forming an indirect VDD and indirect ground path. The static noise margin of 8T SRAM is computed to decide higher stability whilst compared with 6T SRAM. It is inferred that the power of theinewly programmed 8TiSRAMicell is diminished close to 1.5% ias contrasted iwith that of the traditionali8T SRAM cell and ithe stability is improved close to 8.19%. © 2021 Institute of Physics Publishing. All rights reserved.
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JournalData powered by TypesetJournal of Physics: Conference Series
PublisherData powered by TypesetIOP Publishing Ltd