This paper presents design of signed multiplier using various compressors. We have designed 4-3 and 5-3 compressors with two and one signed bit for signed multipliers. This signed multiplier provides low power dissipation and high-speed than a conventional signed multiplier. In addition, we have designed Radix -2 four-point FFT structure using the proposed signed multipliers. We have used 5-3 multicolumn compressor to combine adders and subtractors in the four-point FFT structure. It gives better performance in terms of speed and power. Additionally, pipeline concept has been incorporated in the four-point butterfly structure, which further decrease delay and power. This design was implemented using Cadence RTL compiler with TSMC 90nm technology. © 2017. Eastern Macedonia and Thrace Institute of Technology.