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Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit
A.L. Bhalerao, A. Mane, K. Pensenwar, B.P. Bhuvana, , V.S. Kanchana Bhaaskaran
Published in IOP Publishing Ltd
Volume: 1716
Issue: 1
This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit. © 2021 Institute of Physics Publishing. All rights reserved.
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JournalData powered by TypesetJournal of Physics: Conference Series
PublisherData powered by TypesetIOP Publishing Ltd