This paper presents a low power and high speed 15-4 Compressor for digital signal processing applications. A new 5-3 compressor also proposed which is faster and also consumes less power than the conventional 5-3 compressor. This proposed 5-3 compressor is utilized in 15-4 compressor which will results in low power and high speed. Proposed 15-4 compressor is 11.01% faster and power consumption is reduced by 8.7%.

Marimuthu R

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Balamurugan S

Partha Sharathi Mallick

Pradeepkumar M

Bansal D

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2013 International Conference on Communication and Signal Processing

There are many attempts being made to design circuits in the post-CMOS scenario. One such attempt includes the Nanomagnetic logic. In this logic, a top-down methodology is followed. This paper presents the design of high speed 5:2 and 7:2 compressors using Nanomagnetic logic. © 2019, Springer Nature Singapore Pte Ltd.

Communications in Computer and Information Science VLSI Design and Test

Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic

Compressor adders have lesser critical delay than normal adders, so that they are suitable in multiplier architectures. In multiplication operation, compressors are used for the reduction of partial products to decrease the delay and power dissipation. In image processing operations multiplication is the common operation. In these applications accurate computing is not essential and it can produce meaningful results even it has low accuracy. Approximate computing is used in these image processing and multimedia applications since it is less complex and has low power consumption. Compressor outputs are approximated to produce approximated compressor. Higher bit multiplications require large size compressors. Here four different designs of approximate 15-4 compressor are described. 16 bit multiplier is designed using this compressor. Multiplication of two images on pixel by pixel basis is done with this multiplier. © 2018 IEEE.

2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI)

15–4 Approximate Compressor Based Multiplier for Image Processing

This paper presents the design of approximate 15-4 compressor using 5-3 compressors as basic module. Four different types of approximate 5-3 compressors are used in a 15-4 compressor for less power consumption and high pass rate. We have analysed the results in all the cases. A 16 × 16 bit multiplier is simulated using the proposed 15-4 compressor. Simulation results show that the multipliers with proposed approximate compressors achieve significant improvement in power as compared to the multipliers with accurate 15-4 compressor. Pass rate of the proposed multipliers are high as compared to other existing approximate multipliers. Finally, the proposed multiplier is used in image processing applications, where the peak signal to noise ratio of the image is measured. Quality of the image is compared with an accurate multiplier and the obtained results show that our proposed multiplier performs better than existing approximate multiplier.

Fulltext

IEEE Access

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

Analog Integrated Circuits and Signal Processing

Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12

Parallel pipelined FFT architectures with reduced number of delays

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Journal	Data powered by Typeset2013 International Conference on Communication and Signal Processing
Publisher	Data powered by TypesetIEEE
Open Access	No