This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.

Balamurugan S

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Ravi V

Electronics

School of Electronics Engineering

Chennai Campus

Marimuthu R

Partha Sharathi Mallick

Mk chaitanya v ravi

Ghosh S

Atul, Balakumaran S

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

IEICE Electronics Express

There are many attempts being made to design circuits in the post-CMOS scenario. One such attempt includes the Nanomagnetic logic. In this logic, a top-down methodology is followed. This paper presents the design of high speed 5:2 and 7:2 compressors using Nanomagnetic logic. © 2019, Springer Nature Singapore Pte Ltd.

Communications in Computer and Information Science VLSI Design and Test

Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic

This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error [Formula: see text], normalized mean error [Formula: see text] and normalized mean-square error [Formula: see text] to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research.

Journal of Circuits, Systems and Computers

Error Compensation Techniques for Fixed-Width Array Multiplier Design — A Technical Survey

This paper presents the design of approximate 15-4 compressor using 5-3 compressors as basic module. Four different types of approximate 5-3 compressors are used in a 15-4 compressor for less power consumption and high pass rate. We have analysed the results in all the cases. A 16 × 16 bit multiplier is simulated using the proposed 15-4 compressor. Simulation results show that the multipliers with proposed approximate compressors achieve significant improvement in power as compared to the multipliers with accurate 15-4 compressor. Pass rate of the proposed multipliers are high as compared to other existing approximate multipliers. Finally, the proposed multiplier is used in image processing applications, where the peak signal to noise ratio of the image is measured. Quality of the image is compared with an accurate multiplier and the obtained results show that our proposed multiplier performs better than existing approximate multiplier.

IEEE Access

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

IEEE Transactions on Circuits and Systems I: Regular Papers

Design of Fixed-Width Multipliers With Linear Compensation Function

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Low Error and High Performance Multiplexer-Based Truncated Multiplier

Microelectronics Journal

Low power and high speed multiplier design with row bypassing and parallel architecture

Generalized low-error area-efficient fixed-width multipliers

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Design of low-error fixed-width multipliers for DSP applications

Design of low power fixed-width multiplier with row bypassing

Journal	IEICE Electronics Express
Publisher	Institute of Electronics, Information and Communications Engineers (IEICE)
ISSN	13492543
Open Access	No