This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.
|Journal||IEICE Electronics Express|
|Publisher||Institute of Electronics, Information and Communications Engineers (IEICE)|