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Designing of Power Optimized Bypassing Array Multiplier in Nanometer Technology
Nirlakalla R, Boothuru B.R, Thota S.R, , Talari J.P, Venkata Krishna P.
Published in Springer Berlin Heidelberg
2012
Volume: 270 CCIS
   
Issue: PART II
Pages: 277 - 284
Abstract
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. In this paper Reverse Body Bias (RBB) with high-Vth is used to reduce the leakage power in nanometer technology for the proposed array multiplier with CSA design. The results are carried out by H-Spice for 90nm and 65nm BSIM model files. MTCMOS circuits have shown good results than the conventional circuits. © 2012 Springer-Verlag.
About the journal
JournalData powered by TypesetCommunications in Computer and Information Science Global Trends in Information Systems and Software Applications
PublisherData powered by TypesetSpringer Berlin Heidelberg
ISSN1865-0929
Open Access0