In this speeding world, the fatigue level of people has increased and their sleeping time has decreased. Various studies have registered that 20 % of all the road accidents are fatigue related. The drowsy driver alerting system is a vehicular safety system which will help to prevent accidents that are caused by drivers getting drowsy. This paper aims to use the behavior of the driver, including eye closure and head position. They are monitored by a camera and the driver is alerted if any of these drowsiness symptoms are detected. The software simulation is done through a witty MATLAB code to implement image processing methods for edge detection and determining the complexity value for the image. This code is converted into Simulink block which is further converted into a Verilog code using HDL coder. This gives the modeled hardware architecture which can be integrated as co-processor along with Nios II processor controlling the whole system flow, on a system based on Altera FPGA device. Altera FPGA processes the data in parallel and pipelined manner. © 2018 IEEE.