This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error [Formula: see text], normalized mean error [Formula: see text] and normalized mean-square error [Formula: see text] to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research.

Balamurugan S

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Partha Sharathi Mallick

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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Error Compensation Techniques for Fixed-Width Array Multiplier Design — A Technical Survey

Journal of Circuits, Systems and Computers

This paper presents, low power signed and unsigned fixed-width multipliers using the column bypassing technique with carry save adder array structure. We have decomposed the partial products into two parts and executed them in parallel to reduce the delay of proposed fixed-width array multiplier. The proposed multiplier reduces the power consumption by skipping the unwanted switching activity when the multiplicand operand consists of a number of zeros. This work evaluates the power, delay and area of fixed-width multipliers and shows that the proposed array multiplier consumes less power and has reduced delay compared to the conventional fixed-width array multipliers.

International Journal on Electrical Engineering and Informatics

Fixed - Width Multiplier Circuits Using Column Bypassing and Decompositon Logic Techniques

In this paper, we investigate the design and implementation of standard and fixed-width 8 x 8 multipliers using row bypassing technique. The design is described using VERILOG Hardware Descriptive Language and implemented using XILINX ISE 12.1v tool. Multipliers are a core part of any data path circuit and in many multimedia applications; we require both inputs and outputs to have the same bit width. For these type of applications the standard multipliers is not the best choice because an n-bit input will produce a 2n-bit output. An n-bit output i.e., a fixed width multiplier can be obtained by truncating the least significant partial products of the multiplier. The comparison table shows that a significant reduction of FPGA resources and delay can be achieved using fixed-width multipliers instead of standard multipliers.

Proceedings of the International Conference on Advances in Computing, Communications and Informatics - ICACCI '12

FPGA design and implementation of truncated multipliers using bypassing technique

This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.

Journal	Journal of Circuits, Systems and Computers
Publisher	World Scientific Pub Co Pte Lt
ISSN	0218-1266
Open Access	No