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FPGA design and implementation of truncated multipliers using bypassing technique
Published in ACM Press
Pages: 1111 - 1117

In this paper, we investigate the design and implementation of standard and fixed-width 8 x 8 multipliers using row bypassing technique. The design is described using VERILOG Hardware Descriptive Language and implemented using XILINX ISE 12.1v tool. Multipliers are a core part of any data path circuit and in many multimedia applications; we require both inputs and outputs to have the same bit width. For these type of applications the standard multipliers is not the best choice because an n-bit input will produce a 2n-bit output. An n-bit output i.e., a fixed width multiplier can be obtained by truncating the least significant partial products of the multiplier. The comparison table shows that a significant reduction of FPGA resources and delay can be achieved using fixed-width multipliers instead of standard multipliers.

About the journal
JournalData powered by TypesetProceedings of the International Conference on Advances in Computing, Communications and Informatics - ICACCI '12
PublisherData powered by TypesetACM Press
Open AccessNo