This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

Uma Sathyakam P

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Partha Sharathi Mallick

Singh P.

Fulltext

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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Geometry-Based Crosstalk Reduction in CNT Interconnects

Journal of Circuits, Systems and Computers

Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K.

IET Circuits, Devices & Systems

High-speed sub-threshold operation of carbon nanotube interconnects

In this paper, we propose transmission gates (TGs) as buffers/repeaters for carbon nanotube (CNT)-based VLSI interconnects. Various performance metrics of the TG buffer, viz. propagation delay, crosstalk-induced delay, power dissipation, and power-delay product under super-threshold and sub-threshold conditions are analysed. Performance analysis of TG buffers with CMOS inverter buffers at various interconnect lengths and buffer insertion intervals is done. We have also analysed the performance of Single-wall carbon nanotube (SWCNT) bundle and three different configurations of mixed CNT bundles. By comparing the power-delay product of both the buffers, it is found that TG buffers are more suitable for applications in CNT-based integrated circuits.

IETE Journal of Research

Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

Optimization Techniques for CNT Based VLSI Interconnects — A Review

This paper presents single walled carbon nanotube (SWCNT) interconnects with air as dielectric medium. We treat CNT interconnects as a discrete (fractal) media for the first time where continuum based differential equations fail to capture the physics at nanoscale and hence, we use discrete partial differential equations in this work. We have analyzed the effect of air gaps (AG) on performance factors like temperature dependent resistance R(T) of CNTs and hence the R(T)C delay of the interconnects. We have first calculated the temperature coefficient of resistance (TCR) of CNTs and analyzed the trend of changing resistance at different ambient temperatures. The R(T)C delay shows that CNT/AG interconnects can operate satisfactorily up to 500K. We then compare the R(T)C delay with ITRS predictions from 17nm to 8nm technology nodes. We have also calculated the chip area used by CNT/air-gap interconnects and found that they take up to 83% lesser area than the conventional Cu/low-k interconnects.

Journal of Nano Research

Carbon Nanotube Interconnects with Air-Gaps: Effect on Thermal Stability, Delay and Area

The performance of coupled VLSI interconnects depends on their coupling capacitance and the dielectric medium surrounding them. However, the idea of designing the geometry of CNT bundles to optimize the coupling capacitance is not considered till now. So, in this paper, we model triangular CNT (T-CNT) bundles as VLSI interconnects, for the first time. Factors that reveal the performance of interconnects like propagation delay, crosstalk delay and power dissipated by the interconnects, are simulated in this paper. We do the performance analysis of T-CNT bundle interconnects and conventionally modeled square type CNT bundle interconnects. Upon comparison of the above said metrics, it was found that T-CNT bundle interconnects performed better.

Journal	Data powered by TypesetJournal of Circuits, Systems and Computers
Publisher	Data powered by TypesetWorld Scientific Pub Co Pte Lt
ISSN	0218-1266
Impact Factor	0.337
Open Access	No
Sherpa RoMEO Archiving Policy	Yellow