This paper presents the effect of process parameter variation such as oxide material, oxide thickness, doping concentration along with bias conditions and different high-k dielectric on RF stability performance of Junctionless Tri-Gate Transistor (JLTGT). The small signal RF parameter is obtained from extracted device parameters using TCAD (Technology Computer Aided Design). The results show that optimized JLTGT shows good RF stability performance.

Sivasankaran K

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Kannadassan D

Department of Communication Engineering

Partha Sharathi Mallick

Department of Instrumentation

School of Electrical Engineering

Vyas L

Akshay D

Sharma S.M

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Impact of bias, doping and High-K dielectric on RF stability performance of junctionless tri-gate transistor

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.

Fulltext

Journal of Computational Electronics

Bias and geometry optimization of FinFET for RF stability performance

This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.

Journal of Semiconductors

Stability performance of optimized symmetric DG-MOSFET

This article presents structure and bias optimization techniques for the radio frequency (RF) stability of silicon nanowire transistor. The RF parameters are extracted using device simulation. The device stability is obtained for various bias conditions and geometry, and observed that the proposed device structure shows good stability response. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2114–2117, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27016

Microwave and Optical Technology Letters

Bias and geometry optimization of silicon nanowire transistor: Radio frequency stability perspective

Oxford Music Online

Santa Clara

IEEE Transactions on Semiconductor Manufacturing

CMOS Junctionless Field-Effect Transistors Manufacturing Cost Evaluation

Journal	Data powered by Typeset2015 2nd International Conference on Electronics and Communication Systems (ICECS)
Publisher	Data powered by TypesetIEEE
Open Access	No