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Low - Power and Area - Efficient Square – Root Carry Select Adders using Modified XOR Gate
Published in Indian Society for Education and Environment
Volume: 9
Issue: 5
Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum - output. Inthis paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical Analysis: Usually a Half Adder(HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires onlyone XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives betterresult when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA,Binary to Excess-1 Converter (BEC) based sqrt CSLA and Optimized Logic Based (OLB) sqrt CSLA. The results show thatArea - Delay - Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BECbased sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in ArithmeticLogic Unit (ALU) of a micro-processor as a binary adder.
About the journal
JournalIndian Journal of Science and Technology
PublisherIndian Society for Education and Environment
Open AccessNo