In any general purpose processor the use of conventional full precision multipliers results in increase in the power, area and computational time. So, multipliers being the basic key element of any computation unit take its own importance in decreasing the power as well as increase in the speed. Twin Precision Multipliers has flexible and reconfigurable computational units are creating a trend which overcomes the drawback of the conventional full precision multipliers and also resulting in higher computational throughput of the processors. This paper proposes low power reconfigurable multiplier architecture based reordering of partial products, which reduces the power consumption based on partial products reordering. Reordering of partial products technique is applied on both High Performance Multiplication (HPM) and Dadda column reduction techniques to obtain low power reconfigurable twin precision multiplier.
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|Journal||Data powered by Typeset2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies|
|Publisher||Data powered by TypesetIEEE|