In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.
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|Journal||Data powered by Typeset2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies|
|Publisher||Data powered by TypesetIEEE|