Presented for the first time is an accurate modelling hierarchy for mixed CNT bundle interconnects. Single-walled CNTs and multi-walled CNTs have been modelled as equivalent single conductor transmission lines and then combined to form a mixed CNT bundle interconnect, which is basically a multiple equivalent single conductor model. Two multiple equivalent single conductor interconnects have been taken to form the multiconductor transmission line model. The delays from transient analysis for both models for a unit bundle have been compared with the corresponding ones for SWCNT bundles and MWCNTs that exist in the literature. It is found that mixed CNT bundle interconnects are superior to both SWCNT bundle and MWCNT interconnects in terms of delay.

Uma Sathyakam P

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Partha Sharathi Mallick

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Electronics Letters

In this paper, we propose transmission gates (TGs) as buffers/repeaters for carbon nanotube (CNT)-based VLSI interconnects. Various performance metrics of the TG buffer, viz. propagation delay, crosstalk-induced delay, power dissipation, and power-delay product under super-threshold and sub-threshold conditions are analysed. Performance analysis of TG buffers with CMOS inverter buffers at various interconnect lengths and buffer insertion intervals is done. We have also analysed the performance of Single-wall carbon nanotube (SWCNT) bundle and three different configurations of mixed CNT bundles. By comparing the power-delay product of both the buffers, it is found that TG buffers are more suitable for applications in CNT-based integrated circuits.

Fulltext

IETE Journal of Research

Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects

Carbon nanotube (CNT) interconnects are emerging as the ultimate choice for next generation ultra large scale integrated (ULSI) circuits. Significant progress in precise growth of aligned CNTs and integration of multiwalled CNT interconnects into a test chip make them promising candidates for future nanoelectronic chips. Tremendous research efforts were made on silicon based ultra-low-k dielectrics for Cu interconnects, but, the most recent advancements in polymer based composites as dielectric materials open up fresh challenges in the use of low-k dielectrics for CNT interconnects. This paper reviews the emerging polymer composites like Boron Nitride Nanotubes, Graphene/Polyimide composites, Metal Organic Frameworks and small diameter CNTs. Many reviews are already exists on the synthesis, fabrication, dielectric, mechanical, chemical and thermal properties of these materials. In this review, we have explained the specific properties of these materials and the necessities for integrating them into CNT interconnects to meet the requirements of future IC designers.Keywords: low-k dielectric materials, ultra low-k dielectrics, carbon nanotubes, interconnects, dielectric constant,

Journal of Nano Research

Future Dielectric Materials for CNT Interconnects - Possibilities and Challenges

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

Journal of Circuits, Systems and Computers

Optimization Techniques for CNT Based VLSI Interconnects — A Review

Scaling of integrated circuits leads to increase in design complexity of the transistors. Interconnect delay, Power dissipation and electromagnetic interferences arises due to increase in resistance and capacitance at the nanometer level. Sub threshold operation of devices for ultra-low power requirement necessitates the design issues of interconnects. Carbon nanotube (CNT) interconnects are the better alternative to copper interconnects, mainly due to the excellent properties of carbon nanotubes. CNTs have higher strength and excellent thermal and electrical properties. Current carrying capacity of CNT is nearly 10 6 times that of copper. CNT are basically classified as single walled CNTs and Multiwall CNTs. In this paper, analysis on SWCNT, DWCNT and Mixed CNT bundles as interconnects were done. The performances of mixed CNT bundles are better in delay compared to SWCNT bundles and DWCNT bundles.

2016 International Conference on Communication and Signal Processing (ICCSP)

Mixed CNT bundles as VLSI interconnects

The performance of coupled VLSI interconnects depends on their coupling capacitance and the dielectric medium surrounding them. However, the idea of designing the geometry of CNT bundles to optimize the coupling capacitance is not considered till now. So, in this paper, we model triangular CNT (T-CNT) bundles as VLSI interconnects, for the first time. Factors that reveal the performance of interconnects like propagation delay, crosstalk delay and power dissipated by the interconnects, are simulated in this paper. We do the performance analysis of T-CNT bundle interconnects and conventionally modeled square type CNT bundle interconnects. Upon comparison of the above said metrics, it was found that T-CNT bundle interconnects performed better.

2016 3rd International Conference on Emerging Electronics (ICEE)

Triangular CNT bundles as VLSI interconnects

The change of potential across a CNT in a bundle necessitates the need to consider the inter-CNT coupling capacitance in the equivalent circuit of CNT interconnects for VLSI circuits. This paper presents a realistic inter-CNT electrostatic coupling capacitance and tunneling conductance model for this bundle and studied its effects in detail. The equivalent transmission line circuit model of a unit bundle containing one SWCNT and one MWCNT has been shown. This new model is then used to calculate the delay induced by the inter-CNT capacitance and tunneling conductance, which predicts the relative positioning of MW/SWCNTs in mixed CNT bundle.

Journal	Electronics Letters
Publisher	Institution of Engineering and Technology (IET)
ISSN	00135194
Open Access	No