Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

A mathematical model and experimental analysis of the impact of oxide thickness on the ambipolar conduction in Schottky Barrier Carbon Nanotubes (CNTs) Field Effect Transistor (SB CNTFETs) is presented. Suppression of ambipolar conduction in SB CNTFETs is imperative in order to establish them as the future of IC technology. The ambipolar nature of SB CNTFETs leads to a great amount of leakage current. Employing a gate oxide dielectric of thickness, tox~50 nm suppresses the ambipolar behavior. In an SB CNTFET, it is the electric field at the source/drain contacts that control the conductance and the band bending length at the contacts is defined by tox. Therefore, tox is the prime parameter that influences the width of the Schottky barrier and the current in the subthreshold region. Due to the wide SB, there is a loss in on-current due to tunneling, but the current due to thermionic emission is increased by employing a high-κ dielectric such as Zirconium dioxide (ZrO2). This work proposes an approach to suppress ambipolar behavior in SB CNTFETs without decreasing the on current. The thickness and dielectric constant of the gate oxide are optimized using the particle swarm optimization (PSO) algorithm to achieve suppression of ambipolar conduction without any loss in on-current. The proposed SB CNTFET was modeled using Verilog-A. Experimental demonstration of the suppression of ambipolar property is also presented. Two SB CNTFETs are fabricated using high-κ dielectric such as ZrO2 with different thickness. A device with thin (~5 nm) gate oxide and another device with thick (~50 nm) gate oxide were fabricated. From the experimental results, it is observed that the device with the thin gate oxide exhibited ambipolar characteristics and the device with the thick gate oxide did not exhibit ambipolar characteristics. The increase in thickness, tox, ensures suppression of ambipolar behavior. © 2019 Tech Science Press. All rights reserved.

Electronics

School of Electronics Engineering

Chennai Campus

Electrical

School of Electrical Engineering

Fulltext

Computer Modeling in Engineering & Sciences

Suppression of Ambipolar Conduction in Schottky Barrier Carbon Nanotube Field Effect Transistors: Modeling; Optimization Using Particle Swarm Intelligence; and Fabrication

The objective of this work is to implement a CNTFET-based ternary control unit and a ternary memory to be employed in a ternary processor. Ternary logic gives faster processing speed and Carbon Nanotube Field Effect Transistor (CNTFET) with its ballistic transport and nanometer size ensures low power and less area respectively. A ternary controller circuit is implemented with CNTFETs. C-Element, which is an integral part of the ternary controller circuit, is implemented with CNTFETs. It stores the previous output obtained by it until a new output is attained. This helps the controller to produce outputs according to stored values in the C-Element. The major component for power consumption in processors is the memory. This work also implements a ternary memory with CNTFETs. The simulation outputs with Cadence Virtuoso show superior performance in terms of speed and power when compared to the conventional methods. There is an improvement of at least 70% in the power delay product. By bringing ternary logic and CNTFET together, a low power and high speed processor can be implemented with the control unit and memory presented in this work. © 2017 IEEE.

Department of Biotechnology

School of Bio Sciences and Technology

Vellore Campus

VIT Unitversity

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

Design of CNTFET-Based ternary control unit and memory for a ternary processor

A geometry-physics based compact model for MOSFET-like CNTFET (Carbon Nanotube Field Effect Transistor) is presented. This model is developed in terms of basic geometry parameters like chiral index, doping concentration, number of tubes, pitch etc. This work presents a simpler way to model CNTFET using its energy profile. The non-idealities such as the quantum tunneling, the acoustical/optical phonon scattering in the channel region and the screening effect by parallel CNTs are modeled. The I-V characteristics are obtained over the entire region of operation for large signal (digital) applications. The CNTFET parameters have been optimized for an operating frequency of 500MHz for a channel length of 32nm. Particle Swarm Optimization technique is used to optimize the doping concentration, Nd and the chiral indices (n, m) with an objective to achieve high mobility and low capacitance. The optimal values are obtained for desired pitch and number of tubes. MATLAB and COMSOL are used to model the device and optimize the parameters. © 2016 Elsevier Ltd.

Materials Today: Proceedings

An optimized geometry-physics based compact model of CNTFET

Indian Journal of Science and Technology

Hardware Implementation of CORDIC Power of Two Length DCT

Objective: The objective of this work is to design a Reduced Instruction Set Computing (RISC) processor with Canonic Signed Digit (CSD) recoding. Methods: The incorporation of the CSD recording reduces the number of non-zero bits in the constant word length coefficient. The processor has a dedicated processing unit for the manipulation of floating point numbers. It uses CSD recoded number for the execution of the arithmetic operations such as multiplication. This novel technique reduces the switching activity and in turn resulting in reduction in the power consumed by the processor. Findings: The simulation was carried out using XILINX 14.3 and CADENCE NCLAUNCH. The RISC processor was synthesized with and without the CSD recoding. Although there is a slight increase in the area overhead, the use of ternary number representation in the processor design brought in a power reduction of 56.23%. Conclusions: The CSD recoding was found to be effective in terms of power consumption, making the RISC processor power efficient.

Canonic Signed Digit Recoding based RISC Processor Design

Floating Point High Performance Low Area SFU

FFT Architectures for Real Valued Signals based Different Radices Algorithm

This paper addresses the major challenge being faced by Carbon nanotube field effect transistor (CNTFET) technology in replacing the conventional CMOS i.e. there are no industry standard CAD tools for physical design of CNTFETs. In this paper the standard cells of CNTFET are created using Electric, a CAD design tool. This tool supports the schematic level and layout level entry of CNTFETs upon inclusion of the CNTFET technology library. The physical design of the standard cells is done using Electric and verified by performing DRC, LVS and ERC for the cells designed. © 2014 IEEE.

2014 International Conference on Signal Propagation and Computer Technology (ICSPCT 2014)

Window based design of fractional order FIR digital differentiator using type- III discrete cosine transform

2013 International Conference on Advanced Electronic Systems (ICAES)

Ternary logic implementation and its applications using CNTFET