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Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter
Published in Institute of Electrical and Electronics Engineers (IEEE)
Volume: 7
Pages: 97719 - 97731

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.

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JournalData powered by TypesetIEEE Access
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers (IEEE)
Open AccessYes