The concept of reconfigurable computing facilitates flexibility of the software along with high performance of hardware. The FPGA based hardware provides bit level or fine grain re-configurability where as ASIC based hardware is capable of course grain reconfiguration that lead to accelerated (hardware) performances with lesser re-programming time. This paper presents the implementation of a multiplication accumulation (MAC) unit which is reconfigurable with respect to word lengths of the operands. The unit is capable of processing signed and unsigned numbers as per the requirement. The sub units-multiplier, adder and sign selection units are reconfigurable, can function as independent units and together as accumulation unit. Reconfiguration with word length, throughput or data type is implemented with the help of a set of multiplexers, de-multiplexers and pipeline registers. Two implementations using different adders were compared. One design uses carry save addition in adder module and the other uses ripple carry addition. The implementation using ripple carry adder shows significant improvement in area and power consumption over the other. However, the use of carry save adder gives about 2% improvement on speed than its counterpart. © 2013 IEEE.