Compressors are widely used in multiplier to reduce the partial products. This paper proposed the design of 5-3 multicolumn compressor. The proposed 5-3 multicolumn compressor is used to design the various size multipliers. In this paper, we have designed 6 × 6, 8 × 8, 10 × 10 and 12 × 12 bit multiplier using proposed 5-3 multicolumn compressor, conventional 5-3 multicolumn compressor and conventional 4-2 compressor and compared the results. Simulation result shows that the proposed architecture consumes less power and provides more speed than conventional multicolumn 5-3 compressor and conventional 4-2 compressor. Cadence RTL compiler is used to obtain the results of multiplier.