There are many attempts being made to design circuits in the post-CMOS scenario. One such attempt includes the Nanomagnetic logic. In this logic, a top-down methodology is followed. This paper presents the design of high speed 5:2 and 7:2 compressors using Nanomagnetic logic. © 2019, Springer Nature Singapore Pte Ltd.

Harish R

Mechanical

School of Mechanical Engineering

Chennai Campus

Balamurugan S

Department of Instrumentation

School of Electrical Engineering

Vellore Campus

Marimuthu R

Agarwal S

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic

Communications in Computer and Information Science VLSI Design and Test

One of the recent advances for the beyond complementary metal-oxide semiconductor (CMOS) area is nano-magnetic logic (NML). Many researchers are developing a keen interest in the areas of circuit designing, area optimization and its application in storing the data. Because of its inherent magnetic nature, it can be used to design any magnetic circuit. When compared to the CMOS technology NML logic has potential advantages in terms of non-volatile, low power and radiation in hard. In this paper, we have proposed and implemented a 4-bit squarer circuit using the perpendicular NML (pNML). Squarer design is implemented in MagCAD tool, which embeds design rules, physical models and technological parameters. A register-transfer-level of (VHDL) of the circuit is automatically extracted by MagCAD. The extracted model can be simulated with fast HDL-simulators; this makes it possible to verify the behavior and extract the performance of the designed circuit. This nano-magnetic logic technology is alternative to CMOS technology, which is non-volatile in nature with reduced power consumption. © 2020, Springer Nature Singapore Pte Ltd.

Advances in Intelligent Systems and Computing Soft Computing for Problem Solving

Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD

This paper presents the design of approximate 15-4 compressor using 5-3 compressors as basic module. Four different types of approximate 5-3 compressors are used in a 15-4 compressor for less power consumption and high pass rate. We have analysed the results in all the cases. A 16 × 16 bit multiplier is simulated using the proposed 15-4 compressor. Simulation results show that the multipliers with proposed approximate compressors achieve significant improvement in power as compared to the multipliers with accurate 15-4 compressor. Pass rate of the proposed multipliers are high as compared to other existing approximate multipliers. Finally, the proposed multiplier is used in image processing applications, where the peak signal to noise ratio of the image is measured. Quality of the image is compared with an accurate multiplier and the obtained results show that our proposed multiplier performs better than existing approximate multiplier.

Fulltext

IEEE Access

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.

American Journal of Applied Sciences

DESIGN OF 8-4 AND 9-4 COMPRESSORS FORHIGH SPEED MULTIPLICATION

This paper presents a low power and high speed 15-4 Compressor for digital signal processing applications. A new 5-3 compressor also proposed which is faster and also consumes less power than the conventional 5-3 compressor. This proposed 5-3 compressor is utilized in 15-4 compressor which will results in low power and high speed. Proposed 15-4 compressor is 11.01% faster and power consumption is reduced by 8.7%.

2013 International Conference on Communication and Signal Processing

Design of high speed and low power 15-4 compressor

In this paper, we investigate the design and implementation of standard and fixed-width 8 x 8 multipliers using row bypassing technique. The design is described using VERILOG Hardware Descriptive Language and implemented using XILINX ISE 12.1v tool. Multipliers are a core part of any data path circuit and in many multimedia applications; we require both inputs and outputs to have the same bit width. For these type of applications the standard multipliers is not the best choice because an n-bit input will produce a 2n-bit output. An n-bit output i.e., a fixed width multiplier can be obtained by truncating the least significant partial products of the multiplier. The comparison table shows that a significant reduction of FPGA resources and delay can be achieved using fixed-width multipliers instead of standard multipliers.

Proceedings of the International Conference on Advances in Computing, Communications and Informatics - ICACCI '12

FPGA design and implementation of truncated multipliers using bypassing technique

This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.

Journal	Data powered by TypesetCommunications in Computer and Information Science VLSI Design and Test
Publisher	Data powered by TypesetSpringer Singapore
ISSN	1865-0929
Open Access	No