Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

In deep learning the most significant breakthrough in the field of image recognition, object detection language processing was done by Convolutional Neural Network (CNN). Rapid growth in data and neural networks the performance of the DNN algorithms depends on the computation power and the storage capacity of the devices.MethodsIn this paper, the convolutional neural network used for various image applications was studied and its acceleration in the various platforms like CPU, GPU, TPU was done. The neural network structure and the computing power and characteristics of the GPU, TPU was analyzed and summarized, the effect of these on accelerating the tasks is also explained. Cross-platform comparison of the CNN was done using three image applications the face mask detection (object detection/Computer Vision), Virus Detection in Plants (Image Classification: agriculture sector), and Pneumonia detection from X-ray Images (Image Classification/medical field).ResultsThe CNN implementation was done and a comprehensive comparison was done on the platforms to identify the performance, throughput, bottlenecks, and training time. The CNN layer-wise execution in GPU and TPU is explained with layer-wise analysis. The impact of the fully connected layer and convolutional layer on the network is analyzed. The challenges faced during the acceleration process were discussed and future works are identified

Computer Science

School of Computer Science and Engineering

Chennai Campus

Fulltext

PeerJ ComputerScience

Effect of neural network structure in accelerating performance and accuracy of a convolutional neural network with GPU/TPU for image analytics

Our society has undergone a massive technological revolution over the past decade and electronic appliances have now become ubiquitous. The increase in production of electronic products and the growing inherent need to own the latest technology available has led to a significant increase in the amount of E-waste produced each year. India generated 3.2 million tonnes of E-waste in 2020, with metropolitan cities like Mumbai, Delhi and Bangalore leading the list. Proper management and recycling of E-wastes are critical for the sustainability of any modern city today. While industrial and commercial collection of E-wastes has been in the spotlight, solutions for collection of E-wastes from individual households are limited. This article proposes the implementation of a mobile robot that identifies common electronic wastes based on transfer learning and serves as an attachment to existing municipality garbage trucks. The robot moves around, identifies electronic wastes and performs segregation of the identified material via its arm-based lift and storage mechanism. A convolutional neural network–based identification system has been employed for categorising the E-wastes and yields 96% accuracy. This is a first of its kind attempt, especially in India, to collect and segregate E-wastes from homes and individuals. The system will relieve unskilled labour from the hazardous process while providing a 20% decrease in costs over a 5-year period. The application of this article aims to provide a viable mobile solution for E-waste collection from households with minimal human intervention.

Waste Management and Research: The Journal for Sustainable Economy

Application of artificial intelligence to enhance collection of E-waste: A potential solution for household WEEE collection and segregation in India

Field programming gate array is a semiconductor device used for programming tasks in parallel with greater efficiency and performance that the general core processors present in our desktop. Larger tasks can be parallelized at a much faster rate. The need for more high-performance computing is increasing, especially in the field of cloud after the patches for effects like “Specter” and “Meltdown” have reasonably slowed down the processors in turn affecting the entire cloud, the need for FPGA accelerators have increased [1]. But there are kinds of security attacks on which FPGA makes it vulnerable and harm clouds. In this paper, the various vulnerabilities of FPGAs try to analyze the kind of attacks on FPGA. © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd 2021.

World University root node

Lecture Notes in Networks and Systems

Vulnerability analysis of FPGA through side-channel attacks in cloud

Deep learning for image analytics is widely used in many real-world applications. Due to the rapid growth in data and model size there is a need to distribute the models in multiple nodes. Distributed computing of the model helps to increase the scalability, training time and its cost effectiveness. But the distribution can lead to longer computation times in case of stale nodes. The computational time of the distributed nodes are affected by many factors like latency caused dur to communication, network connectivity, resource sharing, computational power etc. The main problem faced in case of distribution is the staleness among the worker nodes. Effect of stragglers cannot be completely avoided in distributed clusters. The failures in storage, disks, imbalanced workloads, resources sharing etc. are the main cause of stragglers. Stragglers can cause longer computation time and reduce the performance of the model. The different methods used to address this issue is described in the paper in detail. The open research problems in this field are also highlighted. © 2021 IEEE.

Proceedings - International Conference on Artificial Intelligence and Smart Systems, ICAIS 2021

Staleness and Stagglers in Distibuted Deep Image Analytics

The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions.

Journal of Circuits, Systems and Computers

SeRA: Self-Repairing Architecture for Dark Silicon Era

In deep learning the most significant break though in the field of image recognition, language processing was done by Convolutional Neural Network (CNN). The CNN is a powerful algorithm which is capable of using features extraction at multiple levels and this is done based on the distribution of data automatically. The rapid growth in Big Data and the high-performance architectures have made it possible for the growth of CNN. Transfer Learning is the method for performance improvement in the specific problem with the transferring of knowledge learned from other domains. Transfer learning have a wide range of applications and it is widely used in deep learning algorithms There is rapid growth in the use of transfer learning in the pre trained models in CNN. The transfer learning helps to improve the performance of the models and it helps in saving time by acting as an optimization technique. This survey attempts to provide a comprehensive review in understanding the mechanisms of transfer learning and the pretrained models in CNN. © 2020, World Academy of Research in Science and Engineering. All rights reserved.

International Journal of Advanced Trends in Computer Science and Engineering

A comprehensive review of transfer learning on deep convolutional neural network models

Dynamic Voltage and Frequency Scaling (DVFS) approach is proposed to control the power consumption in devices of different types like from a small mobile device to a huge server. This paper aims to study the effect of parallel execution of two benchmark applications, one the Stanford Single Source benchmarks (lightweight parallel code) and, Stanford Parallel Applications for Shared Memory (SPLASH-2) programs (heavy real-Time data streaming parallel applications that run on multi-core clusters) on DVFS for dark silicon ameliorating. Both these benchmarks executed on a gem5 Full System simulator, booting a linaro based linux kernel. To get a holistic big picture of the power and thermal properties of systems that run on DVFS, in addition to the control feature present in gem 5, a power-estimation framework used for the evaluation of the efficiency of various DVFS policies, the MCPAT and Hotspot is also employed. Based on the execution of Stanford workloads DVFS model is analyzed in terms of memory footprint and on other critical processor performance metrics, like running time per core, bus latency, number of read, writes, access time, cache hit or miss. The gem5 is extended with full DVFS support by the addition of a framework in which easy power-model integration can be done.. © 2020 IEEE.

Proceedings - International Conference on Smart Electronics and Communication, ICOSEC 2020

Effect of Parallel Workload on Dynamic Voltage Frequency Scaling for Dark Silicon Ameliorating

Parallelizing pattern matching in multidimensional images is very vital in many applications to improve the performance. With SIMT architectures, the performance can be greatly enhanced if the hardware threads are utilized to the maximum. In the case of pattern matching algorithms, the main bottleneck arises due to the reduction operation that needs to be performed on the multiple parallel search operations. This can be solved by using Shift-Or operations. The recent trend has shown the improvement in pattern matching using Shift-Or operations for bit pattern matching. This has to be extended for multiple dimensional images like hyper-cubes. In this paper, we have extended the Shift-Or pattern matching for multidimensional images. The algorithm is implemented for GPU architectures. The complexity of the proposed algorithm is @ where m is the number of dimensions, n is the size of the array if the multidimensional matrix values are placed in a single dimensional array, k is the size of the pattern and w is the size of the tile. From the result analysis it is found that the performance is maximum, when the pattern size matches the tile size and it is less than 64. This restriction is due to the size of the warp considered. © 2019, Springer Nature Singapore Pte Ltd.

VIT Unitversity

Mechanical

School of Mechanical Engineering

Smart Innovations in Communication and Computational Sciences Advances in Intelligent Systems and Computing

eMDPM: Efficient Multidimensional Pattern Matching Algorithm for GPU

With increasing complexity of processor architectures and their vulnerability to hard faults, it is vital to have self-repairing processor architectures. This paper proposes the idea of autonomic repairing of permanent hard faults in the functional units of an out-of-order processor core using reconfigurable FPGA. The technique proposed utilizes the existing reconfigurable hardware in the new range of embedded systems like Intel Atom E6 × 5C series. The proposed technique includes an on-chip buffer, a fault status table (fully associative) and few control signals to the existing core. To perform self-repairing, decoder will identify reference to the faulty unit and initiate the reconfigurable hardware to be configured as the faulty unit referenced. Dispatch unit will help resolve the reservation station conflicts for the reconfigurable hardware. Execution of instruction that referenced the faulty unit gets executed in the reconfigurable unit. Dispatch unit and the buffers helps complete the out-of-order execution and in-order commit of the instructions that referenced a faulty unit. A hypothetical architecture that loosely resembles ALPHA 21264 is designed as a test bed for analyzing the proposed self-repairing mechanism. Area and time overhead analysis are done using Cadence NCVerilog simulator, Xilinx-Vivado ISE and FPGA Prototype board. Spatial and temporal costs of the proposed design are around 2% and 2.64% respectively. With recent increase in hybrid architectures that has FPGA tightly coupled with ASIC processor core, the proposed solution maximizes the reliability of the processor core without much area and time overhead. © 2019, Springer Nature Singapore Pte Ltd.

Advances in Intelligent Systems and Computing Advances in Computer Communication and Computational Sciences

Self-repairing Functional Unit Design in an Embedded Out-of-Order Processor Core

Energy efficiency is an important aspect of high performance computing today. Energy is the integration of power over time. Power consumption in a system depends on power consumption of processing units, memory and other peripherals. One of the recent advancements in energy efficiency is through parallel computing. Ideally in a system the number of software threads should be equal to the number of hardware threads. But in real time systems the ideal ratio cannot be always maintained. Moreover the ideal value will change depending on the workload and the dynamic characteristics of the system. In this work, a detailed study to understand the effect of multi-threading on power efficiency is carried out. The results of these benchmark analysis show optimal number of threads for different categories of workload, to achieve a fine balance between energy efficiency and performance. These results of the analysed benchmark applications are stored in secondary disks. When a new application is submitted for execution on the system, around 12 characteristics of the submitted application is compared with the analysed benchmark applications. Analysed benchmark application with the least hamming distance from the submitted application is chosen and its corresponding optimal thread value is read from the storage. This data is communicated to the compiler of the submitted application for improving the balance between energy efficiency and performance. For the experimental analysis the compilers of C and Java are used. The results show an improved power efficiency of up to 30% when optimal numbers of threads are used. © BEIESP.

International Journal of Recent Technology and Engineering

Optimized multi-threading to balance energy and performance efficiency

Physically Unclonable Functions (PUF) are hardware blocks implemented for challenge response generation used in many applications including cryptography. Use of hardware block instead of software application helps in improving security matrices PUF can be designed using different types but use of Configurable Ring Oscillator (CRO) block provides many advantages including reduction in area and improved performance matrices. Use of arbiter provides a simple design approach and less area compared to comparators used in the ring oscillator block. A configurable ring oscillator block with arbiter has application in key generation block of many crypto graphical units is proposed in this paper. Monte Carlo simulation used to study the effect of process variation in a design. In this paper Monte Carlo simulation is carried out on CRO block to obtain the results. © 2018 IEEE.

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

2018 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

Ring Oscillator Based Physically Unclonable Function With Arbiter

In recent times, with increased transistor density, it is impossible to verify all the components exhaustively for different scenarios. This results in design bugs also known as extrinsic hardware faults to escape into the processor chip in spite of various levels of testing. Hence, handling design bugs efficiently on the field is a necessity in modern multi-core processors. In this paper, an architecture and algorithm for self-repairing of design bugs in the data path using FPGA is proposed. The FPGA is re-configured during the run-time to take over the functions of the faulty component. To verify the effectiveness of the proposed design a representative sample of five faults are injected and handled. The proposed design's area overhead and time overhead calculations are done using Cadence ncverilog and gem5 simulator respectively. The area overhead of the proposed design is &lt; 1% and performance improvement is around 2.5% compared to the existing techniques. Copyright © 2017 Inderscience Enterprises Ltd.

International Journal of High Performance Computing and Networking

On the field design bug tolerance on a multi-core processor using FPGA

As more and more number of functional units is fabricated on a single chip, the rate of hard faults is increased. To increase the useful life of the chip, an online technique for self-repairing of hard faults is very much needed. This paper proposes an online self-repairing technique for execution unit of an in-order pipelined processor. The proposed method requires a fault table, an on-chip buffer and reconfigurable hardware unit to be included to the existing processor core. The faulty unit details are updated in the fault table. For an instruction that uses any of the faulty unit the decoder will divert it to the Reconfigurable Hardware Unit (RHU). The RHU will be reconfigured on-line to perform the function of the faulty unit. On-Chip Buffer will buffer the configuration bit details needed for the RHU. The experimental evaluation of the proposed design is done using a MIPS processor core. The area overhead of the proposed design is around 7 percent and the time overhead in the presence of faults is around 11 percent. © 2015 Academic Publications, Ltd.