Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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The last decade has seen a quiet uprising in digital video technology. The digital videos are been used in television, broadcasting, Internet and also in mobile phones. The uprising issues use H.264/AVC formats in video compression techniques. The SAD operation can be divided into two stages, viz. absolute and sum stage. Pipelining method is implemented as it is used in low power applications like mobile devices. For checking the functionality, HDL verificationis done by using ModelSim Simulator. This paper represents the idea of yielding a faster outcome than real-time Full-Search (FS) in Motion Estimation (ME) for the main profile/main level of the H.264 standard. In order to generate the outcomes, we use TSMC 45 nm standard-cells library by using Cadence RTL Compiler tool and the obtained frequency of about 176.05 MHz.

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Department of Micro and Nanoelectronics

School of Electronics Engineering

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International Journal of Engineering and Technology

Implementation of SAD architecture for motion estimation in H.264/AVC

This paper aims at the implementation of 16 bit floating point multiplier using Residue Number system. Residue Number System (RNS), which is a non-weighted number system gains popularity in the implementation of fast and parallel computing applications. It has inherent properties such as modularity, parallelism and carry free computation, which speeds up the arithmetic computations. Floating Point can be represented as M × BE where M is Mantissa, E is the Exponent and B is the base. Floating point RNS multiplier consists of RNS Exponent modulo Adder and RNS Mantissa modulo multiplier. In this paper, floating point multiplier will be implemented using Verilog HDL using ModelSim and synthesized using Altera Cyclone II Quartus and frequency of multiplier is found to be 311MHz. © 2013 IEEE.