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22 Publications
14 Journals
Jayakrishnan P
Assistant Professor (Senior)
Department of Micro and Nanoelectronics
pjayakrishnan@vit.ac.in (Work)
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Publications - 22
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Publications (22)
Network (5)
Publications (22)
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Proceedings Article
Structural Analysis of Low Power and Leakage Power Reduction of Different Types of SRAM Cell Topologies
Choudhari S.H
and
Jayakrishnan P
2019 | IEEE
Articles
High throughput systolic array based architecture for fractional motion estimation in hevc video coding
Jayakrishnan P
and
Kittur Harish Mallikarjun
2018 | Institute of Advanced Scientific Research, Inc.
Articles
Improved algorithm for detection of skin and symptoms of skin disease ‘seborrheic keratosis’ with implementation on FPGA and MATLAB
P. Mudgil
,
R. Singla
and
Jayakrishnan P
2018 | Research Journal of Pharmacy and Technology
Proceedings Article
Hardware implementation of template matching algorithm and its performance evaluation
B. Satish
and
Jayakrishnan P
2017 | IEEE
Proceedings Article
ASIC implementation of distributed arithmetic in adaptive FIR filter
S raghunadha reddy
and
Jayakrishnan P
2017 | IEEE
Proceedings Article
Design of area efficient and low power reed solomon decoder
Surabhi B.R
,
Nampoothiri S.N
and
Jayakrishnan P
2016 | IEEE
Journal Article
Open Access
Pipelined Architecture for Motion Estimation in HEVC Video Coding
Jayakrishnan P
and
Kittur Harish Mallikarjun
2016 | Indian Society for Education and Environment
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Proceedings Article
2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation
Jayakrishnan P
and
Kittur Harish Mallikarjun
2014 | IEEE
Proceedings Article
Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit
Bidhul C.B
,
Hampannavar N
,
Joseph Daniel
,
Jayakrishnan P
and
Sivasankaran K
2013 | IEEE
Proceedings Article
ASIC implementation of pipelined ALU
Dave O
,
Yadav D.S
,
...
,
Jayakrishnan P
(4 authors)
2013 | IEEE
Proceedings Article
Implementation of non-linear pipelined floating point adder
Dipu P
,
Hampannavar N.S
and
Jayakrishnan P
2013 | IEEE
Proceedings Article
Implementation of adder structure with fast carry network for high speed processor
Anand N
,
Joseph Daniel
,
...
,
Jayakrishnan P
(4 authors)
2013 | IEEE
Proceedings Article
Implementation of single precision floating point multiplier using Karatsuba algorithm
Mehta A
,
Bidhul C.B
,
Joseph Daniel
and
Jayakrishnan P
2013 | IEEE
Proceedings Article
Design of particle in parallel architecture co-processor for computationally demanding Particle Swarm Optimization Algorithm
Aravind Babu S
,
Babu Ramki S
and
Jayakrishnan P
2013 | IEEE
Proceedings Article
Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture
Kshirsagar R.D
,
Aishwarya E.V
,
...
,
Jayakrishnan P
(4 authors)
2013 | IEEE
Proceedings Article
A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation
Aarthi G
,
Athishkarthic K.S
,
...
,
Jayakrishnan P
(4 authors)
2013 | IEEE
Proceedings Article
A real time multi-bin CABAC encoder for ultra high resolution video
Jayakrishnan P
,
Lincy P.V.A
and
Niyas R.M.
2013 | IEEE
Proceedings Article
A high speed real time multi-bin CABAC encoder for ultra high resolution video
Jayakrishnan P
,
Lincy P.V.A
and
Niyas R.M.
2013 | IEEE
Proceedings Article
High speed architecture for Variable Block Size Motion Estimation in H.264
Jayakrishnan P
,
Niyas R.M
and
Maillikarjun K.H.
2013 | IEEE
Proceedings Article
Design and implementation of low power floating point arithmetic unit
Kukati S
,
Dhanabal R
,
...
,
Jayakrishnan P
,
...
,
Sahoo S.K.
(9 authors)
2013 | IEEE
Showing 1-20 of 22 results
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