Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The proposed LDO does not require an external capacitor making it suitable for System-on-Chip (SoC) applications. The low-frequency PSR of the LDO varies with load current as the transconductance and output conductance of the power transistor depend on the load current. The proposed LDO is capable of maintaining a constant and high PSR for varying loads by using an adaptive network. The NMOS pass transistor in the adaptive network tracks the power-supply noise through the power transistor and bypasses this noise current through it to the ground. This helps to avoid the flow of this noise current through the load and thus the circuit can achieve high and constant PSR for varying loads. The LDO with adaptive network achieves very high power-supply rejections of -125dB at low frequencies and -60dB at 1MHz, for a load current of 4mA. This LDO is implemented in 0.18-μm CMOS technology and consumes 1.35-mW quiescent power over the range of 1-10mA of the load current. © 2020 World Scientific Publishing Company.

Electronics

School of Electronics Engineering

Chennai Campus

Journal of Circuits, Systems and Computers

High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads

In this paper, an internally compensated dual-summed flipped voltage follower (FVF) low drop-out (LDO) regulator is proposed. This LDO uses a small miller capacitance (MC) and an active feed-forward compensation (AFFC) to internally stabilize the feedback loop. The active feed-forward compensator shifts an RHP zero of the miller capacitance to the load-dependent LHP zero. A simple RC high-pass filter enhances the overshoot transient response of the LDO and stabilizes the feedback loop further with increased phase margin. This LDO achieves settling time of 110ns during overshoot and 32ns during undershoot with edge time of 25ns. © 2020 Elsevier GmbH

AEU - International Journal of Electronics and Communications

Dual-summed flipped voltage follower LDO regulator with active feed-forward compensation

A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents IUP1 and IUP2 and pull-down currents IDN1 and IDN2. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage VX. The proposed circuit detects the output voltage via VX and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180nm technology and the simulation result shows that the LDO has good load transient response with 190ns settling time and 170mV voltage spike over 1mA to 100mA load current range. © 2020 World Scientific Publishing Company.

A Cap-less Voltage Spike Detection and Correction Circuit for Low Dropout Regulator

An output capacitor-less flipped voltage follower (FVF) low dropout regulator (LDO) with an active feed-forward compensator is presented. A simple compensator which consists of a miller capacitance and an NMOS pass transistor is used to stabilize the LDO. The miller capacitance places the dominant pole at the gate of the power transistor and provides better transient and small-signal responses than the case when the dominant pole places at the drain of the control transistor. The pass transistor placed between the drain of the control transistor and the output node and provides an additional phase lead by shifting all the significant zeros from RHP to LHP. This compensator extends the unity gain frequency and provides the required phase and gain margin to make the LDO stable. This LDO can drive the load current range 0-50 mA with stable regulated output voltage ranges from 1.2 to 1.6V. The quiescent current of the proposed LDO is (Formula presented.) at a maximum load current of 50 mA. © 2020, © 2020 Informa UK Limited, trading as Taylor & Francis Group.

International Journal of Electronics

A push-pulled capacitor-less FVF LDO with active feed-forward compensator

Objective/Background: Multi-stage CMOS OTAs have been used in vast areas like micro-sensor nodes, Bio-medical applications. In this paper, a three-stage CMOS OTA has been designed in 180 nm technology, which is suitable for low-power applications requiring high driving capability. Methods/Analysis: When both low-power and low-voltage operation are the goals, MOS transistors operating in subthreshold regions are used. So, in this work, all the transistors of the amplifier operate in subthreshold region. Reversed Nested Miller Compensation (RNMC) technique is used for stabilizing the amplifier. A slew-rate enhancer (SRE) is used to enhance the slew-rate of the amplifier after compensation. Findings: Powered with 1-V supply, the proposed OTA can drive loads up to 450 pF with phasemargin for this maximum load as 45°. The maximum gain achieved is 120 dB for low frequencies. Power dissipation is obtained as 275.39 nW for low capacitive loads (200 pF). Cadence Virtuoso-64 tool is used for simulations. Conclusion/Improvements: The problem with slew-rate at higher frequencies has been found to be not at the final stage but at the first stage and is resolved using the SRE circuit for a stabilized three-stage OTA. The stabilized and slew enhanced amplifier can drive up to 450 pF load with around 4 µW power dissipation. © Springer Nature Singapore Pte Ltd. 2018.

VIT Unitversity

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Design of Multi-stage CMOS OTA for Low-Power and High Driving Capability

A low dropout regulator is proposed in this paper. The regulator is designed with classic five pack model to decrease the number of devices and make the design compact and also reduce the power consumption. The system is designed and simulated in cadence virtuoso environment under 180nm technology node. Three models of LDO is proposed in this paper, with all having same error amplifier but with small variations. The advantages and disadvantages of each model will be discussed in the paper. The LDOs have linear characteristic over a good input range. It has good transient response to load variation.

Fulltext

Asian Journal of Pharmaceutical and Clinical Research

DESIGN OF ONCHIP LOW DROPOUT (LDO) REGULATOR FOR POWER MANAGEMENT APPLICATION

Acapacitor-less low drop-out linear regulator with a new compensation technique is presented. A conventional LDO suffers intrinsic stability problem at low load currents and require a large offchip capacitor to make LDO stable. This off-chip capacitor occupies large area in the chip and thus not ideal for SoC applications. Many LDO architectures have been proposed recently but still some of them requires off-chip capacitor and suffers due to bandwidth limitation and requires additional complex circuits. The proposed LDO architecture with a compensation network provides solution to the above problem. The proposed LDO is simulated and verified in Cadence using 180 nm CMOS technology. © 2017 IEEE.