Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Mobile devices are continuously improving, adding integrated sensors, which are of value to the healthcare industry. Sensor-enabled mobile phones collect data from patients, which is useful for doctors in providing immediate care and treatment. As smartphones become ubiquitous, their use as health monitors should become commonplace. This chapter surveys mobile computing devices and sensors in healthcare applications.

VIT Unitversity

Department of Software Systems

School of Computer Science and Engineering

Vellore Campus

Advances in Healthcare Information Systems and Administration Contemporary Applications of Mobile Computing in Healthcare Settings

A Survey of Mobile Computing Devices and Sensors in Healthcare Applications

The current and future computer industry is changing from single core CPU to Multicore Processors. The next generation computing systems are focusing on parallel computing to solve the problem in fast and high speed using parallel programming concepts. By running more than one task at the same time with multiple processors concurrently or parallel we can achieve high speed in our computing applications. Here the performance improvement is measured in terms of increase in the number of cores per machine and is analyzed for better optimal work load balance. The parallel computers follow different workload scheduler. In this paper we investigate how to tune the performance of threaded applications with balanced load for each core or processor. The focus here is the process of comparative analysis of single core and multicore systems to run an application program for faster execution time and optimize the scheduler for better performance

International Journal of Grid and Distributed Computing

Performance Evaluation and Analysis of Parallel Computers Workload

The vending machine is an example of a real time system. There are many vending machines available for public like coffee vending machine, ice cream vending machine, chocolates vending machine and coin vending machine. The use of vending machine for health domain needs a comprehensive study. The pharmacy department of any hospital or clinic needs the transactions to be quick and simplified. In this paper we investigate how to design a vending machine for tablets and medicines. The pills remainder with smart alarm system can be recommended for adult persons who forget to take medicines in time. The enough number of vending machines can be kept in the hospitals or road highways, airports for quick and easy access to tablet and medicine transactions. One of the challenging tasks of ongoing project of smart city is to minimize the number of accidents in the road traffic and install the first aid boxes in regular intervals of highways for easy access of medicines. This can be done by the design of smart vending machines with low budget which can be installed on the roadsides for easy access to everyone. The purpose of this vending machine is to sell the tablets or pills automatically to the patients or needy persons. The payment of this can be by insertion of coins or rupee notes to the machine. This machine has a user friendly interface which displays the menu of basic emergency available tablets or medicines like headache, cold, fever, cottons and bandage, etc. Here we study the design and development process and simulate a program for automatic pill vending machine. © 2016, International Journal of Pharmacy and Technology. All rights reserved.

World University root node

International Journal of Pharmacy and Technology

A new approach towards design and development of smart pills vending machine

Now a day the architecture of high performance systems are improving with more and more processor cores on the chip. This has both benefits as well as challenges. The benefit is running more task simultaneously which reduces the running time of the program or application. The challenges are what is the maximum limit of the number of cores in the given chip, how the existing and future software will make use of all the cores, what parallel programming language to choose, what are the memory and cache coherence issues involved when we increase the number of cores, how to solve the power and performance issues, how the cores are connected and how they are communicating to solve a single problem, workload distribution and load balancing issues in terms of scalability. There is a practical limit for speedup and scalability of number of cores on the chip which needs to be analyzed. So this chapter will focus on the introduction and overviews of parallel computing and the challenges faced in enhancing the performance and scalability in parallel computing architecture.

Advances in Computer and Electrical Engineering Handbook of Research on Advanced Computational Techniques for Simulation-Based Engineering

Challenges Faced in Enhancing the Performance and Scalability in Parallel Computing Architecture

Proceedings of the International Conference on Transformations in Engineering Education

Overview of Effective and Efficient Learning Model Project-Based Learning (PBL)

The computer architecture is a set of disciplines which describes the organization, implementation and functionality of computer systems. It defines how the internal organization of various components and system is designed and implemented to meet the specified capabilities. Computer architecture involves many aspects which includesInstruction Set Architecture, Micro Architecture, Logic Design etc. A computer architecture simulator is a piece of software to model computer devices to predict outputs and its performance metrics on a given input. These simulators can be an instruction set simulator which models a target Microprocessor or a full system simulator whose model includes a processor, a memory system, I/O devices etc. As on today, the instruction set simulator available in the industry uses only a single type of processor (either 8085 or 8086 and so on). This single instruction set simulator has the limitation that at a given time only one type of microprocessor can be simulated between different log-in (any other limitation). To, overcome this, we propose a new integrated computer architecture simulation framework which integrates all microprocessors on a single IDE environment, for better understanding, development, and programming of architecture. © Research India Publications.