Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

This paper presents an analysis on electronic, mechanical and optical properties of cubic titanium dioxide using Orthogonalized Linear Combinations of Atomic Orbitals (OLCAO) basis set under the framework of Density Functional Theory. The structural property, namely lattice constant 'a', and the electronic properties such as, the band diagram, density of states (DOS) have been studied and analyzed. Whereas, the mechanical properties like, bulk moduli, Shear moduli, Young's Moduli, poison's ratio have also been investigated thoroughly. Moreover, optical properties such as refractive index, extinction co- efficient, reflectivity, absorption coefficient have been studied and analyzed thoroughly. The results are compared with previous theoretical and experimental results. It is found that, DFT based simulation produces results which are approximation to experimental results, whereas, the calculated values of elastic constants are better than the previous theoretical and experimental values. © 2019 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of International Conference on Nanotechnology: Ideas, Innovations & Initiatives-2017 (ICN:3i-2017).

School of Electronics Engineering

Vellore Campus

World University root node

Materials Today: Proceedings

A density functional theory based analysis on the electronic, mechanical, and optical properties of cubic TiO2

A PVT compensated sub-µA current reference is proposed in this paper. It is based on the summation of a proportional to absolute temperature (PTAT) current with a complementary to absolute temperature current. The current generators are realized using the subthreshold beta multipliers. The PTAT current generator of the proposed current reference behaves always as PTAT independent of transistor sizing. The process compensation technique is based on the concept of an inverse process dependency between β(= μC OX W/ L) and the threshold voltage V TH of the MOS transistor at any process corner. A current reference of 100 nA is implemented in CMOS 0.18 µm technology and studied through simulation. The proposed circuit has a temperature coefficient of 335 ppm/°C in the temperature range of 0–100 °C. It provides a low process variation of ± 2.1% and a lower line sensitivity of 0.093%/V in the supply voltage range of 1.35–3 V. It achieves a better figure of merit of 5.487% compared to the current references reported in the literature. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Analog Integrated Circuits and Signal Processing

A PVT compensated nano-ampere current reference in 0.18 µm CMOS

Mobile Ad Hoc Networks (MANET) are typically wireless networks that do not have any fixed network architecture. This makes the task of routing layers difficult. A popular reactive routing protocol – Ad hoc On-demand Distance Vector (AODV) used in MANETs has certain vulnerabilities which make it susceptible to black hole attacks. This paper proposes an innovative technique to detect and prevent the possibility of a black hole attack in AODV based MANETs. Using the approach of detecting multiple Route Reply (RREP) messages, authentication of nodes is done by the use of a randomly generated id unique to each route discovery process. This method was tested using simulations in NS2 software and compared with previous attempts. The proposed method showed marked improvement in performance in the presence of malicious nodes.

Department of Embedded Technology

International Journal of Innovative Technology and Exploring Engineering Regular Issue

Random ID based Secure AODV to prevent Black Hole Attack in MANET

Arithmetic units such as adders and multipliers play an essential role in the performance of Digital signal processor (DSP) systems. The efficiency of the Processors are influenced by the speed and power consumption of arithmetic units. It is improved by adopting approximate computing in arithmetic units with acceptable degradation in the output. Approximate computing is an emerging topic in the past decades, it aims to achieve promising design approach with the sacrifices in computational quality for error resilient applications. Approximate computing can be adopted both in hardware level and software level of research. This paper provides an elaborative investigation about approximate computing on full adders which is explored at the hardware level. The approximation is applied to full adders either at gate level or transistor level. Further, ripple carry adder is designed for varying bit width with different degrees of approximation using these approximate Full adders. Ripple carry adder is estimated based on the structural analysis such as Area, Delay Product (ADP) and Power, Delay Product (PDP) and error matrix such as pass rate, error rate, Normalized Error Distance (NED) and Mean Error Distance (MED). The ripple carry adders are designed in Verilog HDL and stimulated in Synopsys Design Compiler (DC) using tsmc 65 nm standard cell library typical corner whereas, the error characteristics is done in MATLAB. © 2019, Springer Nature Singapore Pte Ltd.

VIT Unitversity

Communications in Computer and Information Science VLSI Design and Test

A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications

This paper presents a brief information on the ASIC implementation of adaptive finite impulse response (FIR) filters based on pipelined distributed arithmetic (DA) architecture. The pipelined sum of partial products of input samples is stored in the lookup table of the DA. The area of the proposed design is reduced by replacing the adder of the shift accumulation unit with the carry-save adder. The throughput rate of the design is increased by having fast clock to the carry-save adder and slow clock to the remaining circuit. The proposed design is implemented in Synopsys 90 nm CMOS technology. The area delay product (ADP), minimum cycle period (MCP), and energy per sample are reduced when compared with the conventional DA-based architectures. © Springer Nature Singapore Pte Ltd. 2019.

Lecture Notes in Electrical Engineering Microelectronics, Electromagnetics and Telecommunications

ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Wireless sensor networks have gained immense significance and popularity in modern technology especially as a result of emerging concepts like the Internet of Things (IoT). These networks are usually under constant pressure to scale-up in order to meet the ever-growing demand. Under such situations, it is often required to connect two existing adjacent, but independent, networks so that they form a single larger network. Some of the networks may even have mobile nodes. This paper proposes an effective method for placing a bridge node in the intersection of coverage region of two networks using a combination of Steiner tree algorithm and concept of edge nodes—Edge-based Three-Point Steiner (EdTPS) tree—such that communication across the network can be carried out with the shortest possible path. © Springer Nature Singapore Pte Ltd. 2019.

Computer Science

School of Computer Science and Engineering

Chennai Campus

Wireless Communication Networks and Internet of Things Lecture Notes in Electrical Engineering

Shortest Path Solution to Wireless Sensor Networks Using Edge-Based Three-Point Steiner Tree Concept

this paper is presenting the findings of project work that involves finding more efficient and faster circuit logics to bring down the clock skew. Clock skew is the instantaneous difference between the readings of two clocks arrival time. Clocks are used to drive many individual units in a circuit i.e. they are required at many points throughout the circuit at the same time. The problems pertaining to transportation of clock signals are that a fraction of current reaches millions of transistors (because of fan-out) and the clock reaches far away units at a delayed time. Both these problems can be rectified by using efficient clock inverter and clock buffer circuits. Clock skew can be reduced by either increasing delay in the faster clock path to match the slower path or by reducing the delay in the slower path by improving driving strength. To match the arrival times, tunable clock buffers and clock inverters will be designed. This paper presents speed efficient circuits for clock buffers and clock inverters which can be implemented in the pre (clock tree synthesis stage) CTS. Pre and post layout analysis are done and results are obtained using cadence tools considering sample NOC router architecture. Clock buffer designed using gpdk 045 node and compared with the proposed clock buffer of 45 nm node. The timing slack of the designed standard cells improves by 45.9% and power consumption decreases by 2.09%. © 2019 IEEE.

2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies, ICICICT 2019

High Performance Clock Path elements for Clock Skew reduction

Department of Instrumentation

School of Electrical Engineering

International Journal of Materials and Product Technology

Editorial

This paper investigates the RF Stability performance of the Double Gate Junctionless Tunnel Field Effect Transistor (DGJL-TFET). The impact of the geometrical parameter, material and bias conditions on the key figure of merit (FoM) like Transconductance (gm), Gate capacitance (Cgg) and RF parameters like Stern Stability Factor (K), Critical Frequency (fk) are investigated. The analytical model provides the relation between fk and small signal parameters which provide guidelines for optimizing the device parameter. The results show improvement in ON current, gm, ft and fk for the optimized device structure. The optimized device parameters provide guidelines to operate DGJL-TFET for RF applications. © 2019, Science and Information Organization.

Fulltext

International Journal of Advanced Computer Science and Applications

Performance Analysis of Double Gate Junctionless Tunnel Field Effect Transistor: RF Stability Perspective

The excess switching activity during testing increases the power dissipation beyond the normal operation of the circuit. The non-linear power distribution creates localized heating called hotspot which results in the structural damage and increased cooling package cost. The temperature of a particular block depends on heat generation and dissipation of the circuit blocks. The uniformity in power distribution among the circuit blocks is the key requirement for temperature reduction. The unspecified bits present in the test patterns are utilized to reduce the switching activity during testing. In this paper, we present an event-driven based power analysis and temperature aware X-filling to reduce the total power dissipation among the circuit blocks in such a way to reduce peak temperature. To reduce the peak temperature, the power dissipation of each block is monitored with the help of fillings the X-bits. The experiments are carried out with the ISCAS’89 benchmark circuit and show a significant reduction in peak temperature and ensure uniform power distribution during testing. © 2019, Gazi University Eti Mahallesi. All Rights Reserved.