Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

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IET circuit devices and systems

A low power and soft error resilience guard-gated Quatro based flip flop in 45nm CMOS technology

The energy consumption of the devices or circuits built on the IoT's is becoming a significant concern with the complementary metal oxide semiconductor (CMOS) technology scaling. To reduce energy consumption, supply voltage (VDD) scaling has proved to be an effective technique with near-threshold/subthreshold computations depicting the endpoint of voltage scaling. This paper discusses how the near-zero computing (NZC) is achieved by scaling the VDD beyond the subthreshold regime using the negative capacitance FET (NCFET) to enable IoT with beyond CMOS features. After characterising the NCFET for near zero operation, the basic computational circuits: Logic gates and 1-bitfull adder circuit are designed and simulated using NCFET at near-zero VDD of 0.1 V. In comparison with the CMOS counterparts, the NCFET logic designs have achieved significant improvements and is found that the NCFET logic results in more than 54%, 68%, 85%, and 95% savings in power, delay, energy, and EDP respectively. © 2021 Inderscience Enterprises Ltd.. All rights reserved.

World University root node

International Journal of Intelligent Enterprise

Near-zero computing using NCFET for IoT applications

In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to reduce area and latency. Moreover, normalised energy consumption and area delay product are reduced by 32%, and speed is increased by 5.2 times compared to prior works. Further, the fixed-point word-length is optimised to minimise the area without affecting the accuracy. © 2020 Elsevier B.V.

Integration

A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition

Electron transport through a few-donor cluster flanked by acceptors is studied by first-principles and semi-empirical simulations in gated Sinanowire transistors with n+ electrostatically-doped source/drain. Local density-of-states spectra are probed by electrical characteristics at room temperature for clarifying modifications induced by acceptor-atoms on the energy states of the few-donor cluster. It is found that acceptor-atoms located between the few-donor cluster and the leads mainly shift the cluster potential, introducing a minor distortion to its energy spectrum. The results change only weakly as the acceptor-atoms are moved towards the Si nanowire surface, and systematically depend on the number of acceptors. © 2021 The Japan Society of Applied Physics.

Applied Physics Express

Electron transport via a few-dopant cluster in the presence of counter-dopants in silicon nanowire transistors

This paper presents a low power architecture for linear periodically time varying (LPTV) filter by decomposing into finite computational threads. An N-tap, M period LPTV filter architecture is minimized into a single LTI filter by enabling the thread decomposition (TD) of the LPTV filtering operation. The proposed architecture is a generalization to the transposed form structure. A new insight, derived from TD enabled this generalization, which is otherwise not possible. Implementing the LPTV filter with multiplier less functional blocks based on binary common sub-expression elimination (BCSE) algorithm reduced the critical path delay. Experimental results show that the proposed design offers 48.9% reduction in area delay product (ADP) and 14.2% reduction in power delay product (PDP). The LPTV filtering operations in various applications can be realized with the proposed architecture. This work is the first attempt to the ASIC implementation of an efficient architecture for LPTV filter. © 2021, Springer Nature Singapore Pte Ltd.

Lecture Notes in Electrical Engineering

ASIC Implementation of Linear Periodically Time Varying Filter by Thread Decomposition

In this paper, a detailed study and analysis on the electronic and optical properties of anatase, rutile and brookite titanium dioxide (TiO2) which are the naturally occurring phases of TiO2 have been carried out. We have obtained these properties using the self-consistent orthogonalized linear combination of atomic orbitals with meta-generalized gradient approximation (MGGA) and Tran and Blaha (TBO9) as exchange-correlation under the framework of density functional theory. Obtained results on band gap value (E g), dielectric constant and refractive index as calculated by considering the optimal value of c (system-dependent parameter) have been analyzed statistically and are found to be much closer to the experimental values and are better than the other approaches published in the literature. It is seen that optical absorption for all the three phases of TiO2 occurs in UV region of EM spectrum. Using statistical analysis in correlation with other effective methods such as mBJ, GGA + U, GGA + Ud + Up, LSD + U, GW and HSE06 functional, it is found that MGGA-TB09 gives a better description of electronic structure and optical properties with less computation time. This work provides good understanding of electronic and optical properties of TiO2, stems a foundation for its possible applications in photo catalytic activities of dye sensitized solar cells. © 2020 IOP Publishing Ltd.

Modelling and Simulation in Materials Science and Engineering

Investigating the naturally occurring forms of TiO2on electronic and optical properties using OLCAO-MGGA-TBO9: A hybrid DFT study

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs. © TÜBİTAK

Turkish Journal of Electrical Engineering and Computer Sciences

Dual bit control low-power dynamic content addressable memory design for IoT applications

Approximate computing-based hardware is directed towards reduction in area and power consumption; it finds better suitability in various image processing applications. In order to achieve low complexity, approximate techniques are applied in the arithmetic units which provide promising results in enhancing the performance of DSP processors with optimal degradation on its accuracy. In this paper, two approximate full adder designs are proposed, namely, the first design as proposed approximate full adder 1 (PAA1) and the second design as proposed approximate full adder 2 (PAA2). In both the designs, the approximation on the Boolean expressions is carried out to reduce the hardware complexity with the significant tolerance on the error rate. Also, a multi-bit approximate carry select adder is proposed with the utilization of PAA1 and PAA2, respectively. The performance of the proposed adders is analyzed in terms of parameters like gate count, structural synthesis, error, and also in terms of image metrics. The proposed and existing designs are synthesized using Synopsys Design Compiler with TSMC 65 nm technology for better comparison. Synthesis results indicate that the proposed 16-bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA. The image metrics results also validate that the proposed adder with highest peak signal-to-noise ratio is highly adoptable for image processing applications. © 2021 John Wiley & Sons, Ltd.

International Journal of Circuit Theory and Applications

An error efficient and low complexity approximate multi-bit adder for image processing applications

The tailoring the band gap energy of the ternary Indium Gallium Nitride (InxGa(1−x)N) alloy shows a good spectral match with a range of wavelength in electromagnetic spectrum and provided a new approach for its utilization in Photovoltaic solar cells. In this paper a 2D numerical simulation of Indium Gallium Nitride (InxGa1−xN) single junction solar cell using TCAD has been presented. The device has been simulated and analyzed using physical models such as Auger recombination models using Fermi–Dirac Statistics, Shockley–Read–Hall recombination models and Band Gap Narrowing effect. The J–V and P–V characteristics of the device in dark and illuminated condition were analyzed. The single-junction In0.72Ga0.28N solar cell shows the maximum efficiency under normalized AM 1.5 G, 0.1 W/cm2 and at a temperature of 300 K. Further, figure of merits depending on different mole fraction of Indium, like short current density (Jsc), Open circuit Voltage (Voc), fill factor (FF), maximum power generated (Pmax) and conversion efficiency of the designed solar cell has been extracted. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.

Optical and Quantum Electronics

TCAD based performance assessment of Indium Gallium Nitride based single junction solar cells for different mole fractions of Indium

Purpose: Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach: Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings: The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW. Research limitations/implications: A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications: The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value: The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power. © 2020, Emerald Publishing Limited.