Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDB-HDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO2 below the channel and source, HfO2 beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (JDC) and source-channel (JSC) junctions and improves ON-current (ION). The buried oxide above the degenerated P+ substrate determines the tunneling width at the JDC and minimizes the ambipolar current. The device simulations show a low OFF-current (IOFF) of 4.21× 10−17 A/μm, a greater ION of 4.12× 10−4 A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO2− SiO2 gate oxide. The above-mentioned result enables the device to be opted for low power applications. © 2020, Springer Nature B.V.

World University root node

School of Electronics Engineering

Vellore Campus

Silicon

Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors

Color Space Conversion (CSC) in image processing applications, demands computationally simple floating point multipliers consuming less area and power. This necessitates the design and realization of the same meeting the aforesaid concerns. This paper makes one such contribution in the form of a New Bit Pair Recoding (NBPR) algorithm for realizing a Data Length Reduction (DLR)-based 16-bit Half-Precision Floating Point Multiplier (HPFPM). This algorithm with merged partial product addition achieves partial product height reduction from n to n4 for an n × n multiplier by evading 2’s complement, negative encoding and sign extension. HPFPM is implemented on both Application Specific Integration Circuit (ASIC) with TSMC 180, 130 and 65 nm technologies and Xilinx-Virtex-5 and Virtex-7 Field Programmable Gate Array (FPGA) families. HPFPM synthesized on TSMC 65nm consumes 51% and 55.8% of area and power respectively, with 0.6835% error when compared with full width half-precision multiplier. Also, HPFPM for RGB-YUV-RGB and RGB-YCbCr-RGB conversion reduces the area, power consumption by 11%, 12% respectively, with 93.2% improved accuracy, when compared with truncated 32-bit single-precision floating point multipliers (SPFPMs). The converted image is evaluated using Peak-Signal-to-Noise-Ratio (PSNR) and Mean Square Error (MSE) in Matlab for quantifying HPFPM suitability for CSC in imaging. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Multimedia Tools and Applications

Efficient half-precision floating point multiplier targeting color space conversion

In this paper, a Self-consistent Orthogonalized linear combination of atomic orbitals (OLCAO) technique with a generalized gradient approximation such as Perdew-Burke-Ernzerhof Solid (GGA-PBE SOL) has been used to scrutinize the structural, optical, electronic and mechanical properties of normal pressure phase (Anatase and Rutile) and high pressure phase i.e., cubic (Fluorite and Pyrite) TiO2. Electronic and optical properties of normal pressure phases of TiO2 are also investigated using (Meta) MGGA-Tran and Blaha (TB09) and obtained results are a close approximation of experimental data. It is seen that the virtually synthesized structural parameter for cubic and tetragonal phases of TiO2 are consistent with experimental and theoretical data. From the effective mass of charge carriers (m∗), it can be observed that pyrite TiO2 is having lower effective mass than the fluorite and hence shows higher photocatalytic activity than fluorite. Furthermore, it is seen that fluorite is more dense than anatase, rutile and pyrite TiO2. From the theoretical calculations on the optical properties, it can be concluded that optical absorption occursin the near UV region for high and normal pressue phases of TiO2. Again from the reflectivity characteristics R(ω), it can be concluded that TiO2 can be used as a coating material. Elastic constants, elastic compliance constants, mechanical properties are obtained for anatase, rutile, fluorite and pyrite TiO2. A comparison of the results with previously reported theoretical and experimental data shows that the calculated properties are in better agreement with the previously reported experimental and theoretical results. © 2020 The Author(s). Published by IOP Publishing Ltd.

Fulltext

Materials Research Express

Comparative study on structural, electronic, optical and mechanical properties of normal and high pressure phases titanium dioxide using DFT

This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared. © 2020 World Scientific Publishing Company.

Surface Review and Letters

TCAD SIMULATION and PERFORMANCE ANALYSIS of SINGLE and DUAL GATE OTFTs

Communication of images has become very easy and frequent due to popularity of internet. But this fast moving world is prone to various threats from unauthorized users. To protect images and maintain privacy of data many data hiding and encryption techniques are developed. In this paper, a novel reversible 2-stage data hiding algorithm with chaotic based encryption using DNA encoding is proposed. Firstly, Integer Wavelet Transform (IWT) is applied on cover image to convert it from spatial to transform domain. Then, 1st level of data hiding is carried out using threshold based histogram shifting algorithm. Resultant image is interpolated to double of its size and second level of data hiding is done using adaptive prediction error expansion. This stego image is scrambled using chaotic logistic map, result is then DNA encoded using complementary rules. The encoded image is then XOR with a key image generated using hash function and chaotic map. Finally, encrypted image is obtained by DNA decoding the image. Simulation results obtained show the algorithm gives good embedding capacity; also the encrypted images are validated against key sensitivity, statistical and differential attacks. © 2020 IEEE.

Department of Communication Engineering

Proceedings of the 5th International Conference on Inventive Computation Technologies, ICICT 2020

Secured Data Transmission through Dual Domain Reversible Data Hiding and Encryption in Images

Because of globalization in the semiconductor industry and manufacturing processes, integrated circuits are more exposed to harmful attacks called hardware Trojan. This can be considered as a serious threat to the Integrated circuits. Due to the inclusion of hardware Trojan into the existing circuit, it causes the possible effects like changing the functionality of the circuit and discharges some-secret information to the attacker. In this paper, we designed a hardware Trojan, which consists of two parts namely Trigger used to activate Trojan and payload, which changes the functionality of the chip normally the payload is an XOR gate. 2K×(K-1) Trojans are generated for a one-line trigger merged with one payload line for a circuit with K signal lines. The Trojan is detected by generating test patterns by using standard ATPG Tools which detects conditional stuck-at faults-and allows us to find the Trojan coverage and in addition to that this model is effective in finding out the real Trojans. © 2020 IEEE.

2020 IEEE International Test Conference India, ITC India 2020

Modeling and test generation for combinational hardware trojans

To improve the transconductance of operational transconductance amplifier (OTA), various architectures namely recycling folded cascode (RFC), Improved recycling folded cascode (IRFC), modified recycling folded cascode (MRFC) and high recycling folded cascode (HRFC) are existing in the literature. In this paper, further improvement in the transconductance of MRFC OTA can be achieved by shorting two nodes of its current mirror and is proposed as high modified recycling folded cascode (HMRFC) amplifier. The performance of the proposed HMRFC OTA is compared with the existing state of art OTAs. To validate the progressions in the specified parameters, recycling folded cascode (RFC), modified recycling folded cascode (MRFC) and high modified recycling folded cascode (HMRFC) OTAs are realized and implemented in UMC 180 nm process technology using Cadence Spectre for a bias current of 1.2 mA. Simulation results indicate that the proposed amplifier exhibits a DC gain of 79.47 dB, the slew rate of 194.2 V/µSec, UGB of 285.85 MHz and phase-margin of 77.12o for a load capacitance of 5 pF and also observed that the CMRR and FoMs of the proposed amplifier are better by a factor of 1.3 and 1.5 in comparison to RFC, and by a factor of 1.27 and 1.41 in comparison to MRFC OTAs respectively. © 2020, Paulus Editora. All rights reserved.

Engineering and Applied Science Research

Design and analysis of modified recycling folded cascode amplifier with improved transconductance and slew rate

The non-invasive heart rate of the fetus is of great relevance for clinical measures to detect health fluctuations of the fetus during pregnancy. The electrocardiogram (ECG) is often used to detect cardiovascular malformations and heart disorders in the patient. An ECG is not able to measure fetal pulse rate because it shows a low signal-to-noise ratio due to the movement of the fetus in relation to midriff of the mother. The proposed work is based on effective removal of noise components, detection of normal sinus rhythms and arrhythmias of the fetus. Fluctuations in heart rate indicate the disease arrhythmia, i.e. either low or high heart rate. The main goal of this research is to provide an independent component analysis method for removing the maternal ECG(m-ECG) from the selected ECG signal to obtain the fetal ECG(f-ECG). Joint Approximation Diagonal Eigen Vector (JADE) is an algorithm used to discriminate the different components within the signal. The separated f-ECG is used for peak detection and feature extraction. The arrhythmia is detected from the extracted features. The proposed technique has been evaluated with 17 samples and an accuracy of 94.11% is achieved. © 2020 IEEE.

2020 7th International Conference on Smart Structures and Systems, ICSSS 2020

Diagnosis of fetal arrhythmia using JADE algorithm

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, (Formula presented.). This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field (Formula presented.) and (Formula presented.), respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs. © 2020 John Wiley & Sons, Ltd.