Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

Coefficient decimation filter banks (CDFBs) found its application in software defined radio (SDR) channelizers because of its advantages such as highly reconfigurable and low complexity (number of multiplications). Multiplier-less realization is highly preferable when the ultimate goals are implementation simplicity and processing speed. This paper presents a design of multiplier-less CDFB where coefficient space of filters belongs to sum of powers-of-two (SOPOT) form. To obtain, the SOPOT approximations of impulse response values of the CDFB sub filters, a modified version of vector successive approximation (SA) technique termed as Matching Pursuits Generalized BitPlanes (MPGBP) algorithm is utilized. Design examples show that the computational time and implementation complexity (number of adders) of the proposed CDFB is lower than those of its counter parts. © 2020, Research Trend. All rights reserved.

World University root node

School of Electronics Engineering

Vellore Campus

International Journal on Emerging Technologies

Design of successive approximation (Sa) based low complexity multiplier-less coefficient decimation filter bank for sdr receivers

In this paper, a novel programmable operational transconductance amplifier (POTA) using a pseudo resistor based programmable attenuator is proposed. A 4th order Butterworth programmable low pass filter (LPF) targeted for biomedical applications is designed using the proposed POTA. The proposed POTA and the LPF are designed and implemented in 0.18 ​μm CMOS technology with a supply voltage of 1 ​V and their performances are evaluated through post-layout simulations. The proposed POTA consumes a power of 27 ​nW, and its transconductance could be varied from 27 ​nA/V to 75 ​nA/V. It has higher linearity, dynamic range (DR) of 85.62 ​dB–79.46 ​dB and lower input-referred noise (IRN) of 33.15 μVrms to 58.65 μVrms than pre-input voltage attenuator based OTAs. The proposed LPF consumes a power of 208 ​nW. Its output dynamic range and IM3 lie in the range of (62.1 ​dB–49.26 ​dB) and (61.87 ​dB–53.14 ​dB) respectively. Its cutoff frequency can be varied from 100 ​Hz to 250 ​Hz. © 2020 Elsevier Ltd

Microelectronics Journal

A novel programmable attenuator based low Gm-OTA for biomedical applications

For continued scaling with silicon, the stacked nanosheet field-effect transistor (SNSH-FET) is considered to be a major candidate for sub-7-nm technology. The radiofrequency (RF)/analog performance of a three-channel SNSH-FET is studied herein and benchmarked against a fin-shaped field-effect transistor (FinFET) at 7-nm technology and having the same footprint on the wafer. In the existing SNSH-FET on a bulk substrate, the source/drain junction formed on the bulk substrate contributes extra capacitance. An SNSH-FET structure with a source/drain-on-insulator (SDOI) configuration is presented herein, incorporating an extra channel (channel 4) on the bulk. Channel 4 has a supersteep retrograde (SSR) doping profile, which is achieved by placing a 10-nm-thick lightly doped silicon layer (SSR buffer layer) on the ground plane or a punchthrough-stopper (PTS) doped Si substrate. The parasitic source/drain junction capacitance and leakage under channel 4 are alleviated by growing a 10-nm-thick insulator layer before the in situ doped source/drain epiregion (a configuration referred to as SDOI). The presented structure has the same capacitance as the existing three-channel SNSH-FET on a PTS-Si substrate but with a 6% enhanced drive current, thereby achieving an improvement in terms of the delay and RF/analog performance. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.

Journal of Computational Electronics

A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors

This work investigates the performance of the inverted-T (IT) junctionless (JL) FinFET with selective buried oxide (SELBOX) topology. The electrical characteristics of SELBOX-ITJL FinFET are analyzed and compared with the ITJLFinFET. The performance of the SELBOX-ITJL FinFET is estimated for different SELBOX lengths (LSELBOX), substrate doping, UTB thickness (tsi). SELBOX-ITJL FinFET exhibits better ION, ION/IOFF, SS and DIBL for LSELBOX ≈ gate length (Lg). Unlike ITJL FinFET, substrate doping empowers to engineer the threshold voltage (VTH) of the proposed device. ION of the SELBOX-ITJLFET is improved by 48% and 9% compared to JLFET and ITJLFET respectively. Performance of SELBOX-ITJL FinFET at high temperatures (up to 550 K) is illustrated. The self-heating effect in SELBOX device is also studied and it is observed that the proposed device exhibits better immune to self-heating as compared to ITJL FinFET. Virtual device modeling and extensive device simulations are carried out using Synopsys Sentaurus TCAD tools (sprocess &amp; sdevice). © 2019, Springer Nature B.V.

Silicon

Process Variation Study of SELBOX Inverted- T Junctionless FinFET for High-Performance Applications

In recent times, the role of FINFET devices is increasing in the field of RF-IC design for realizing the high frequency circuits. As a result, high frequency characteristics including RF stability needs to be investigated carefully. Hence this work presents the impact of device geometrical and process parameter variations on the RF stability of 20 nm SELBOX Inverted-T Junctionless FINFET (SELBOX ITJLFET). The stability factor (K), critical frequency (fk) and its dependency on small signal parameters (SSP) are investigated by varying the device and process parameters like Gate Workfunction (GWF), fin height (Hfin), fin width (Wfin), Source underlap spacer length (LUS) and SELBOX length (LG). In addition, the relation between the bias and the stability factor of the device is also studied to identify the bias operating point in a stability perspective. From the simulation results, it is found that larger the SELBOX and LUS, lower the critical frequency and thereby making the device unconditionally stable at lower frequencies. Finally, an optimized design guideline is proposed, which makes the device suitable for high bandwidth applications. © 2020, Springer Nature B.V.

Impact of Device Geometrical Parameter Variation on RF Stability of SELBOX Inverted-T Junctionless FINFET

The solutions to the problem of the tracking a wireless node is approached conventionally by: 1) proximity detection; 2) triangulation; 3) scene analysis methods. In these, scene analysis method is simple, accurate and less expensive. Indoor localisation technologies need to address the existing inaccuracy and inadequacy of global positioning-based systems (GPS) in indoor environments (such as urban canyons, inside large buildings, etc.). This paper presents a novel indoor Wi-Fi tracking system with minimal error in the presence of barrier using Bayesian inference method. The system integrates an android app and python scripts (that run on server) to identify the position of the mobile node within an indoor environment. The received signal strength indicator (RSSI) method is used for tracking. Experimental results presented to illustrate the performance of the system comparing with other methods. From the tracked nodes, a theoretical solution is proposed for finding shortest path using Steiner nodes. © 2020 Inderscience Enterprises Ltd.

Department of Embedded Technology

Computer Science

School of Computer Science and Engineering

Chennai Campus

Fulltext

International Journal of Computer Aided Engineering and Technology

Improved indoor location tracking system for mobile nodes

The energy storing element, inductor plays a vital role in CMOS based high frequency integrated circuits, especially in signal generation and impedance matching blocks.An on chip inductor is considered as a critical component because its performance directly impacts the associated circuitry when it is used as a load device or as a matching element. Out of the various requirements of an inductor which resides inside a chip, the inductance value,quality factor and self resonance frequency with smaller area is often preferred. This paper focuses on the lumped model of inductors for high frequency circuits working in the Millimeter wave region from 30 GHz to 300 GHz. For millimeter wave oscillators,inductance value in the range of pico Henry are essential and hence a complete model of an inductor is presented. Using electromagnetic simulator SONNET, all the parameters are extracted. The extracted model is used in the design of an LC Oscillator for millimeter wave band. A Q factor of 26 is achieved for an inductor value close to 153 pH at 60 GHz.The circuits employing this inductor shows promising results when simulated using 45 nm CMOS pdks. © 2020, North Atlantic University Union. All rights reserved.

International Journal of Circuits, Systems and Signal Processing

Design of on chip spiral inductors for millimeter wave frequency synthesizers

The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-Type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p-n junction formed at the drain-substrate junction acts as a reverse-biased tunnel diode during biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain-substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels' configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance. © 1963-2012 IEEE.

IEEE Transactions on Electron Devices

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

In literature double recycling folded cascode operational transconductance amplifier (DRFC-OTA) is realized to achieve higher transconductance. To realize preamplifier for bio-medical applications, it is necessary to design an OTA with lower noise. In this paper source degeneration is adopted for DRFC-OTA for further reduction of noise and is proposed. To access the efficacy of this technique, the preamplifier using DRFC-OTA with source degeneration (DRFCSD) is realized in UMC 180 nm technology and is studied through simulations. For sizing the transistors of DRFCSD, gm/ ID methodology is adopted. From the simulation results it is observed that, the preamplifier exhibits a mid-band gain of 40.02 dB at − 3 dB bandwidth of 5.69 Hz–5.45 kHz. The total input referred noise of amplifier is found to be 3.27μVrms for 5.69 Hz–5.45 kHz for a power consumption of 1.53μW. The noise efficiency factor is found to be 1.58 and provides an output swing of 1.2 Vpp at THD of 1 %. CMRR and PSRR of the preamplifier are simulated and found to be 66.55 dB and 54.99 dB respectively. The amplifier occupies an area of 0.16mm2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.

Analog Integrated Circuits and Signal Processing

A power efficient low-noise source degenerated bio-potential amplifier

This paper presents the negative differential resistance (NDR) behavior of an MoS2 armchair nanoribbon double-gate field effect transistor. The large peak-to-valley current ratio (PVCR) of 2.58 × 102 with a peak current value of − 0.8 μA is achieved with the presented device configuration. A 5-nm channel length device was considered for the study and an extended Hückel model with nonequilibrium Green’s function method is used for the simulation. A phosphorus atom is used as a substitutional dopant at the sulfur site of the MoS2 field effect transistor near the source and drain regions. The PVCR of the device can be controlled by applying a gate voltage. The achieved subthreshold slope of the device is 88 mV/decade with Ion/Ioff value of 1011 at 300 K. The other parameters such as peak current and NDR voltage window are analyzed. The proposed device configuration shows the potentiality of MoS2 armchair nanoribbon material for future small length scale electronic device applications. © 2019, The Minerals, Metals & Materials Society.