Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

Department of Control and Automation

School of Electrical Engineering

Vellore Campus

VIT Unitversity

School of Electronics Engineering

Advances in Intelligent Systems and Computing Soft Computing for Problem Solving

Optimal Control of Roll Axis of Aircraft Using PID Controller

In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5-point DFTs. Foremost, the proposed PE architecture for the 5-point DFT computation is designed by factorising the 5-point DFT computation operation into 2 × 2 cyclic convolution units and then the 2- and 3-point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5-point PE designs, the PE can start its operation only after the arrival of all the five-input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5-input PE. © The Institution of Engineering and Technology 2020

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Electronics Letters

Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates, which operate on qubits. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement and additionally, it is capable of detecting single bit error. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in Modelsim software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs. © 2020 IEEE.

International Conference on Emerging Trends in Information Technology and Engineering, ic-ETITE 2020

Single Bit Fault Detecting ALU Design using Reversible Gates

Compensating the error using additional circuitry is mandatory in a low-error fixed-width multiplier. Instead of compensating the error, reconfiguring n-bit fixed-width multiplier to n/2-bit error-free full-width multiplier using decomposed multiplication is proposed in this paper. The decomposed block multiplication using an area-efficient New Bit Pair Recoding (NBPR) algorithm in fixed-width mode shows a relatively lesser truncation error than existing truncated multipliers. Reconfigurable 16☓16 NBPR multiplier in three different modes (8☓8, 16☓8, 16☓16) with a fixed 16-bit product is verified on the TSMC 65nm CMOS standard cell library. The experimental results show that the NBPR multiplier consumes a lesser area than standard Booth multipliers. Evaluating the proposed multiplier in imaging shows improved PSNR with minimal error compared to other fixed-width multipliers. © 2020, Gazi University Eti Mahallesi. All rights reserved.

Gazi University Journal of Science

Low-error reconfigurable fixed-width multiplier for image processing applications

The performance of a system depends on the performance of its components, and the component’s performance depends on the effectiveness of the function performed by it. The logarithmic function is one of the most commonly used functions in the communication world. Lately, the implementation of logarithmic function is done using BJTs and MOSFETs in their weak inversion layer, but still, there is a scope for the improvement in the parameters like power, cost, speed, area and complexity. In this paper, the design for implementation of logarithmic function is proposed, and this is done by the use of three basic mathematical operations: (i) differentiation (ii) division and (iii) integration. Here, all the circuits performing such basic operations are being designed using OTA so that it can handle different arbitrary signals in a systematic manner in order to reduce the complexity of the system. Simulations of all the circuits have been done using SPECTRE. © 2020, Springer Nature Singapore Pte Ltd.

Department of Smart Computing

School of Information Technology and Engineering

Department of Information Technology

Nonlinear System Modelling Using Programmable Hardware for Soft Computing Applications

The main focus of present study is to optimize the extraction parameters for maximum yield of biomass, β-carotene and chlorophyll content and their antioxidants from Kappaphycus alvarezii by response surface methodology (RSM) along with adaptive neuro-fuzzy inference system (ANFIS). Central composite rotatable design of RSM was applied to optimize the effect of microwave-assisted extraction (MAE) parameters. In this way, four parameters, such as methanol concentration (X1: 65–80%), microwave power (X2: 15–20%), radiation induced temperature (X3: 45–60 °C) and radiation exposure time (X4: 7.5–15 min) at five levels were selected. Optimal conditions were found as X1 = 80%, X2 = 20%, X3 = 45 °C and X4 = 12.5–14.5 min, under this condition, % yield of biomass (y1) = 86.231–87.212%, β-carotene and chlorophyll content (y2) = 77.348–82.841 mg/gm, %DPPHsc (y3) = 69.362–72.768%, %ABTSsc (y4) = 66.282–70.621%, FRAP (y5) = 62.654–64.381 μg mol (Fe(II))/g has been obtained. Also, optimized values of MAE parameters were compared and verified with ANFIS. Further, the major bioactive compounds present in the optimally obtained extract of K. alvarezii was identified through FTIR, gas chromatography-mass spectrum and HPLC. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Department of Thermal and Energy Engineering

School of Mechanical Engineering

Journal of Food Measurement and Characterization

Optimization of bioactive compounds extraction assisted by microwave parameters from Kappaphycus alvarezii using RSM and ANFIS modeling

Steganography is the process of hiding secret information in other multimedia files, like image, audio and video, such that any unauthorized person does not have any clue of the hidden secret data. Due to the recent computational advancements, there has been an increased risk in secure communication and thus, steganography has become one of the most researched domains in information security. In this paper, a novel method of steganography is approached where the cover image is scrambled using graph theory; then the secret data is embedded in the LH, HL and HH planes using LSB embedding of the cover image after applying Haar forward transform to get the embedded image. The secret data hidden in the cover image is first converted to a QR-like (Quick Response) image and then to be embedded in the cover media. The stego image is obtained after reverse Haar transform and descrambling of the embedded image. The proposed method when applied to a set of grayscale images, not only gave us stego images with greater embedding capacity but also high Peak Signal to Noise Ratio (PSNR) and a low Mean Square Error (MSE) and very appreciable Normalized Cross-Correlation (NCC) along with a good Structural Similarity Index Matrix (SSIM) when compared to the cover images.

Department of Communication Engineering

Universal Journal of Electrical and Electronic Engineering

QR-like Secret Data Hiding in Integer Wavelet Transform Domain Images

A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 µA. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it may be noted that the proposed amplifier achieves a gain of 76.24 dB and unity gain bandwidth of 74.7 MHz with an input referred noise and slew rate of 139.2 µVrms and 64.05 V/ µs respectively. The proposed amplifier occupies an area of 2760 µm2 © TÜBİTAK.

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES

Modified recycling folded cascode OTA with enhancement in transconductanceand output impedance

Network intrusions detection is a continuous vigilant task and to efficiently analyze the traffic in the corporate network to detect network intrusions. The efficiency of the Network Intrusion Detection System (NIDS) performance can be improved by adopting feature selection or reduction process to suit the present day high speed real time networks. This work is focused on identifying the key features of the audit dataset used to build an efficient light-weight NIDS. The NSL KDD dataset is used in this work titled Attribute Richness Based Feature Selection (ARFS) in order to analyze its performance.The obtained results are compared with the Correlation-based Feature Selection (CFS) and Information Gain (IG) feature selection methods. The proposed feature selection method produced better detection rate comparatively.

Department of Software and Systems Engineering

International Journal of Engineering and Advanced Technology Special Issue

High-Performance Feature Selection Model for Network Intrusion Detection System

Wireless Sensor Networks contain an incredible number of hubs with limited registering, detecting, and wireless communication capacities. These systems have been utilized as a part of a wide zone of utilizations, such as human services, contamination checking, and target-following frameworks. The dynamic clustering of sensors into bunches is a prevalent procedure to expand the system lifetime and increment adaptability. To accomplish this, in this article the sensor hubs are adjusted to ensure a long lifetime and the activities are arranged into rounds that use fixed time intervals. In the first phase, a clustering topology is found, and a group head is picked in view of the outstanding energy level. Then the cluster head screens the network energy threshold value to identify the energy drain rate of all its cluster members. In the second stage, the Long-Lifetime and Low-Latency Data Aggregation Scheduling method is used. This scheduling method assigns schedule openings to group part information parcels. Here, congestion occurrence is completely kept away from the scenario. In the third stage, an Energy-Efficient Distributed Schedule-based convention is used to keep up greatest residual energy level over the network. The experimental outcome shows the steps proposed in this article ensure an increase in the network lifetime and decrease in the energy utilization. © 2019 by ASTM International