Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

One of the semiconductor device fabrication processes include annealing, a process by which silicon wafer is heated at higher temperature for a certain duration and then cooled down slowly. The main purpose of annealing is to mend the damage caused by ion implantation and to increase the electrical activation of dopant atoms. Traditionally, annealing has been used to enhance the material properties and electrical characteristics of conventional semiconductors devices made from silicon and gallium arsenide which found applications in normal human environment. Being a wideband gap semiconductor with noble physio thermoelectric properties, silicon carbide has been a choice of material for higher temperature and higher-power applications. Due to inertness to chemical reaction at nominal temperature, ion implantation is reported to be a preferred method for doping silicon carbide. As the ion implantation causes material destruction a suitable annealing scheme is required for recovering crystal damages and dopant activation. In this paper, effect of different annealing scheme viz. post implantation annealing, post deposition and post metallization annealing on the electrical and structural characteristics of silicon carbide-based devices reported till date are reviewed comprehensively. © 2020, World Academy of Research in Science and Engineering. All rights reserved.

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International Journal of Emerging Trends in Engineering Research

Profound understanding of various annealing scheme effects on the electrical characteristics of silicon carbide based devices

Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leakage through gate oxide reduces memory retention time and reliability of gate dielectric. Knowledge of conduction mechanisms of gate leakage current is essential for the optimization of process conditions to reduce leakage current and determination of suitable operating voltage of flash memory devices. In this work, conduction mechanisms contributing to gate leakage current in SiC MIS capacitors with different gate dielectric are extracted for the entire range of the gate electric field. Space charge limited (SCL) conduction mechanisms either Ohm’s law or trap filled limit process or combination of both are observed to be dominant at the low electric field. Hopping conduction found to be dominating the leakage current when the slope of leakage current changes from the lower value to a higher value. The sequence of mechanisms contributing to gate leakage current from low electric field to high electric field is found to be same in SiO2 annealed in O2 and N2, SiON and Al2O3/SiON stack. The trap filled limit process, trap-assisted tunneling and FN tunneling are dominating the gate leakage current at low, mid and high electric field respectively in all the investigated MIS capacitors. © 2019, © 2019 IETE.

IETE Journal of Research

Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors

Silicon carbide as a wide band gap semiconductor with attractive electrical and thermo physical properties has found its applications in high temperature, high power and radhard environment. However, silicon carbide MOS devices suffer from higher density of interface states than similarly oxidized silicon/SiO2 interface. Improving the interface and electrical characteristics of silicon carbide MIS/MOS structure suitable for the above said applications is the current focus of the researcher. In this work, thin body silicon carbide MOSFET with buried oxide has been designed using TCAD and its electrical characteristics has been analyzed. Comparison of drain, transfer and capacitance voltage characteristics with conventional silicon carbide MOSFET reveals that thin body with buried oxide has improved the performance of MOSFET with higher gate capacitance, higher drive current and gain than conventional structure. Proposed SiC MOSFET with buried oxide exhibit higher gain with stable threshold voltage as the thickness of the body increases. Further, the proposed device exhibit higher field effect mobility than conventional MOSFET. © BEIESP.

International Journal of Innovative Technology and Exploring Engineering

Design and simulation of thin body silicon carbide MOSFET with buried oxide

Purpose: Al2O3 used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors. Design/methodology/approach: Al2O3 film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N2 at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al2O3/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field. Findings: RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al2O3/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions. Originality/value: The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al2O3/SiC capacitors suitable for flash memory applications is investigated in this paper. © 2018, Emerald Publishing Limited.

Microelectronics International

Effect of post deposition annealing and post metallization annealing on electrical and structural characteristics of Pd/Al2O3/6H-SiC MIS capacitors

HfO 2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO 2 /SiC capacitors offer higher sensitivity than SiO 2 /SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO 2 /SiC interface. Effect of post deposition annealing in N 2 O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO 2 /SiC MIS capacitors are reported in this work. N 2 O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N 2 result in formation of Hf silicate at the HfO 2 /SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40 min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N 2 O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO 2 /SiC capacitors. © 2017 Elsevier B.V.

Applied Surface Science

Improvement on the electrical characteristics of Pd/HfO 2 /6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

Effect of post metallization annealing on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors are reported in this work. MIS capacitors when subjected to post metallization annealing in forming gas for longer duration (40 min) exhibited improved electrical characteristics. Density of interface states is found to be reduced by one order. Gate leakage current density is also reduced for the devices when compared with those MIS capacitors for which annealing was carried out for only 10 minutes. Minimum value of interface state density is extracted to be 6.5 ×1010 /cm2 eV and gate leakage current density of 0.47 A/cm2 is obtained at an electric field of 5 MV/cm in devices which have undergone annealing for extended duration. Conduction mechanisms contributing to leakage current in the entire range of gate electric field are also extracted and presented in this paper. Major mechanism of conduction at low electric field is determined to be Trap assisted tunneling, while Fowler-Nordheim tunneling is dominating at high electric field. © 2016 IEEE.

2016 3rd International Conference on Emerging Electronics, ICEE 2016

Effect of post metallization annealing on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors and extraction of conduction mechanisms

Silicon carbide MIS capacitors with high dielectric constant material and its stack has been designed and characterized using TCAD Sentaurus tools. Interface dipole theory on metal-dielectric interface has been used to determine the work function of gate metal on different dielectric materials. It has been found that in single dielectric with high-K material Si3N4 exhibit better electrical characteristics with fixed oxide charges and interface state density of - 3.06 × 1012 / cm2 and 2.9 × 1012 /cm2 eV respectively. In high-K stack dielectric, extracted fixed oxide charges is found to be lowest in Si3N4-SiO2 stack while HfO2-SiO2 stack exhibit lowest interface state density of 3.0 × 1012 /cm2 eV. Gate current density of stack dielectric at high electric field is compared with SiO2 and is found to be lowest in ZrO2-SiO2 stack dielectric. © 2014 IEEE.