Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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The low-power current feedback instrumentation amplifier (CFIA) circuits using local feedback configuration are reported in the literature for biomedical applications. However, they have limitations such as low gain, higher area, and higher noise due to the need for higher source degeneration resistors (in tens to hundreds of kΩ), and higher minimum achievable bandwidth (in tens of kHz). In this paper, a low-power, low-noise CFIA using closed-loop configuration is proposed to overcome these limitations. It uses a folded cascode operational transconductance amplifier with a lower value of source degeneration resistor (in the order of few kΩ) in the input stage to reduce the noise without compromising the loop gain. As the bandwidth of the proposed CFIA is defined as unity-gain bandwidth of the CFIA’s loop gain, it can be reduced below 10 kHz without increasing area. The proposed CFIA is designed and implemented in a 0.35 µm CMOS process for a current of 9.6 µA with a supply voltage of 3 V, and its performance is evaluated through simulation. It has a gain of 34 dB, total input-referred noise of 3 µVrms, and a noise efficiency factor of 3.81. It achieves a bandwidth of 8.8 kHz using a load capacitor which is more than four times smaller than that of local CFIA. It provides an input signal swing of 16 mVpp at THD of 1% and the CMRR of 118 dB. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

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Circuits, Systems, and Signal Processing

A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier

Capacitors realized using symmetric floating impedance scaling (SFIS) are area efficient. They are preferred for the implementation of fully differential filters for biomedical applications. The SFIS reported in the literature has poor accuracy and lower effective bandwidth. In this paper, a cross coupled symmetric floating impedance scaling (CC-SFIS) with enhanced bandwidth and accuracy is proposed. To evaluate its performance, a 500 pF capacitor is implemented in UMC 180 nm CMOS technology with a base capacitor (Cb) of 10 pF using both CC-SFIS and source follower based SFIS (SF-SFIS). The magnitude and phase of the impedance of the capacitor realized using CC-SFIS and SF-SFIS are obtained through post-layout simulations. CC-SFIS requires 53.68% lower area, 62.39% lower power consumption, and 88% higher accuracy than SF-SFIS. Fully differential 2nd order Butterworth low pass filters with cutoff frequency of 100Hz are implemented in UMC 180 nm technology using both CC-SFIS and SF-SFIS capacitors. Their performances are evaluated through simulation. From this, it is found that the deviation in the cut off frequency of the filter using CC-SFIS is smaller (2%) compared to that using SF-SFIS (40%) circuit. © 2020 Elsevier GmbH

AEU - International Journal of Electronics and Communications

A cross-coupled symmetric floating impedance scaler with enhanced bandwidth and accuracy

In this paper, a novel programmable operational transconductance amplifier (POTA) using a pseudo resistor based programmable attenuator is proposed. A 4th order Butterworth programmable low pass filter (LPF) targeted for biomedical applications is designed using the proposed POTA. The proposed POTA and the LPF are designed and implemented in 0.18 ​μm CMOS technology with a supply voltage of 1 ​V and their performances are evaluated through post-layout simulations. The proposed POTA consumes a power of 27 ​nW, and its transconductance could be varied from 27 ​nA/V to 75 ​nA/V. It has higher linearity, dynamic range (DR) of 85.62 ​dB–79.46 ​dB and lower input-referred noise (IRN) of 33.15 μVrms to 58.65 μVrms than pre-input voltage attenuator based OTAs. The proposed LPF consumes a power of 208 ​nW. Its output dynamic range and IM3 lie in the range of (62.1 ​dB–49.26 ​dB) and (61.87 ​dB–53.14 ​dB) respectively. Its cutoff frequency can be varied from 100 ​Hz to 250 ​Hz. © 2020 Elsevier Ltd

Microelectronics Journal

A novel programmable attenuator based low Gm-OTA for biomedical applications

A Source Follower based Symmetrical Floating Impedance Scaler (SF-SFIS)circuits are reported in the prior works, which realize large capacitors with the low area for a fully differential filter. In this paper, a novel Flipped Voltage Follower based Symmetrical Floating Impedance Scaler (FVF-SFIS)with high accuracy is presented. The proposed circuit based on flipped voltage follower with cascaded current mirrors can detect low base capacitors which have lower area and power than the prior SF-SFIS circuits. In order to evaluate its performance and comparison, a 500 pF capacitor is realized by multiplying the base capacitor of 10 pF using both FVF-SFIS and SF-SFIS methods. The magnitude and phase of these impedance scalers are obtained through post-layout simulation. It is found that the proposed impedance scaler requires 51.58% lower area, 69.23% lower power dissipation, and 91.33% higher accuracy than the SF-SFIS. The accuracy of the proposed FVF-SFIS is compared with SF-SFIS circuit by designing a 3rd order Chebyshev low pass filter (LPF)using FVF-SFIS and SF-SFIS with cut-off frequency 100 Hz. The circuit has been designed and simulated in UMC 180 nm technology. © 2019 Elsevier GmbH

Fulltext

Area and power efficient flipped voltage follower based symmetrical floating impedance scaler with improved accuracy for fully differential filters

A PVT compensated sub-µA current reference is proposed in this paper. It is based on the summation of a proportional to absolute temperature (PTAT) current with a complementary to absolute temperature current. The current generators are realized using the subthreshold beta multipliers. The PTAT current generator of the proposed current reference behaves always as PTAT independent of transistor sizing. The process compensation technique is based on the concept of an inverse process dependency between β(= μC OX W/ L) and the threshold voltage V TH of the MOS transistor at any process corner. A current reference of 100 nA is implemented in CMOS 0.18 µm technology and studied through simulation. The proposed circuit has a temperature coefficient of 335 ppm/°C in the temperature range of 0–100 °C. It provides a low process variation of ± 2.1% and a lower line sensitivity of 0.093%/V in the supply voltage range of 1.35–3 V. It achieves a better figure of merit of 5.487% compared to the current references reported in the literature. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Analog Integrated Circuits and Signal Processing

A PVT compensated nano-ampere current reference in 0.18 µm CMOS

In this paper, an inductorless wideband balun-low noise amplifier (LNA) using current source loads, common-mode feedback (CMFB), asymmetric capacitive cross-coupling (CCC) and auxiliary common-source amplifier are proposed to obtain low noise figure (NF) and high gain. The asymmetric CCC boosts the gain and reduces the NF. The CMFB fixes the output to a common mode voltage. RMS detectors are proposed to realize a low-cost built-in self-test (BIST) circuit for measuring the gain of the LNA during its entire lifespan. The proposed balun-LNA is implemented in 0.18 µm CMOS process technology and the performance is studied through post-layout simulations. PVT and Monte Carlo simulations are performed to check for the robustness and yield of the circuit. From these analyses, it is found that the integrated average gain of the LNA obtained with and without the RMS detectors is 19.1 dB and 20.1 dB respectively in the 3 dB-band of 0.18–2 GHz. NF of the LNA in this band is 2.87 dB. The average IIP3, IIP2, and 1 dB compression points of the LNA are (−4.89 dBm, +28.57 dBm, −20.42 dBm) respectively. The proposed LNA dissipates a power of 4.9 mW with a supply of 1.2 V and requires an area of 0.04 mm2. © 2019

High-gain inductorless Wideband Balun-LNA using asymmetric CCC &amp; BIST using RMS detectors

In this paper, a novel current reference circuit using a single beta multiplier is proposed. To achieve better process compensation, some identical series connected transistors with optimum aspect ratios are proposed for the generation of both PTAT and CTAT currents. Diode connected cascode transistors are proposed for the generation of the bias voltage for these transistors to reduce the area and power dissipation. The proposed current reference circuit is designed and implemented for a current of 100 nA at 50°C, using UMC 180nm CMOS process technology and simulated. The proposed circuit has a lower temperature coefficient (124.5 ppm/°C in the range 0°C - 100°C), lower line sensitivity (0.35%/V over a supply voltage range of 1.253 V) and lower process variation of |0.3%| compared to those reported in the literature. It requires lower total current as well as area and has the best figure of merit of 1.645 %. © 2019 IEEE.

2019 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2019

A 0.450 μW 125 ppm/°C PVT compensated 100nA current reference in 0.18 μm CMOS technology

This paper proposes a low noise amplifier (LNA) which can be reconfigured to operate in two frequency bands at low power. The LNA employs self-cascode devices in current-reuse configuration to enable lower supply voltage operation without compromising the gain. A quasi-differential structure is used to achieve high linearity and good common-mode rejection. The proposed LNA is designed to operate in (3.1–4.7 GHz: Band1) and (5.0–7.2 GHz: Band2) in the 5G frequency spectrum. It is implemented in 65 nm UMC-LL CMOS process technology using 0.6V, and its performance is evaluated using post layout, PVT and Monte Carlo simulations. The proposed LNA requires an area of 0.03276 mm2. The power dissipation, maximum gain, minimum noise figure, average IIP3, IIP2 of the LNA operating in Band1 and Band2 are found to be (0.97 ​mW, 17.6 ​dB, 2.20 ​dB, +0.72dBm, +46.49dBm) and (0.485 ​mW, 12.1 ​dB, 3.31 ​dB, +0.12dBm, +42.60dBm) respectively. © 2019 Elsevier Ltd

Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G

In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series–series and shunt–shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5–22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz–4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz–10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.

A low-power low-noise and high swing biopotential amplifier in 0.18 µm CMOS

Threshold Inverter Quantizer (TIQ) based ADC with thermometer code is proposed in the literature as an alternative to traditional flash ADC for low power applications. TIQ based ADC suffers from threshold variations due to process. In this paper, a novel TIQ based ADC with gray code is proposed.The architecture is also made tolerant to the process variations. For the purpose of evaluating its efficacy, a 4-bit ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology at a supply voltage of 1 V and studied through simulation. The proposed ADC achieves a maximum sampling rate of 300 MS/s for an input signal with 1 V swing and has a power consumption of 122 μW. The power dissipated by the proposed ADC is lower compared to those reported in the literature. The proposed ADC exhibits INL of 0.0622 LSB, DNL of 0.0444 LSB, SNDR of 25.227 dB and ENOB 3.89 bits respectively. It has a better FoM of 0.027 pJ/conversation step. The proposed scheme reduces the deviation of the inverter threshold by 98.75% compared to that of normal inverter. © 2015 IEEE.

2015 3rd International Conference on Signal Processing, Communication and Networking, ICSCN 2015

A 4 bit low power process tolerant flash ADC in 0.18μm CMOS

Inverter based comparators are proposed in the literature for medium speed ADCs with low power and low area requirements. The comparator is succeeded by a buffer in order to boost the gain of the comparator. This requires an additional delayed clock which limits the speed of the ADC. To overcome this limitation, a modified inverter based comparator which uses a single clock signal is proposed in this paper. The analog input is converted to gray codes first and then to binary codes. It dispenses with power hungry thermometer to binary code converter. For evaluating its efficacy, a 4-bit ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology at a supply voltage of 1.8 V. The proposed ADC achieves a maximum sampling rate of 100 MS/s for an input signal with 1.8 V swing and has a power consumption of 1.08 mW. The power dissipated by the proposed ADC is lower compared to those reported in the literature. The proposed ADC exhibits INL of 1.36 LSB, DNL of 1.04 LSB, SNDR of 23.59 dB and ENOB 3.62 bits respectively. It has a better FoM of 0.87 pJ/conversion step. © 2015 IEEE.