Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

In wireless communication system, the supply voltage should be as low as possible to increase operation time of the system. This shows how importance the low-power circuits are in this field. Recently, there has been considerable interest in the use of Fin type Field Effect Transistor (FinFET) technology to implement RF components such as low-noise amplifiers (LNAs), mixers, and voltage-controlled oscillators (VCOs). VCOs are critical building blocks in modern wireless communication system which is mainly used in Phase Locked Loop. This work describes designing and simulation of Double Gate (DG) FinFET based Inductor (L) and Capacitor (C) tank VCO and the radiation effect of single event transient (SET) on the topology. The LC VCO topology is implemented with 30 nm DG-FinFET technology with 1V as DC power supply voltage which oscillates at 32.61 GHz frequency, results the VCO draws 64.97 μA current and an average power consumption of 64.97 μW. The measured phase noise of the topology is -120.54dBc/Hz at 1 GHz offset frequency and Figure of Merit (FOM) is - 162.68 dBc/Hz at 1 GHz offset frequency.

VIT Unitversity

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Indian Journal of Science and Technology

IRadiation Induced SET Impact on DG-FINFET based LC-VCO Design

Memristor is a nanoscale device whose existence was predicted by Leon Chua in the year 1971. It is considered to be the fourth passive circuit element apart from inductor, capacitor and resistor. It is a resistor with memory which realizes the missing relation between charge and flux. In this paper, basic active filters using memristor are presented. Simulation of high pass, low pass and band pass filters are performed using the Voltage Threshold Adaptive Memristor (VTEAM) model as a tunable load. The change in cut-off frequency and gain of active filters with different memristor configurations are investigated. The use of memristor makes the gain and cut off frequency of the filter adjustable. © 2016 IEEE.

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS)

Application of memristors in active filters

As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. The Sensitivity of ICs to soft errors emerge as reliability threat which motivates significant interest in the development of various techniques both at the device and circuit level for SEU hardness in SRAM memories. To facilitate the scaling the concept of underlap Gate- Source/Drain (G-S/D) was suggested in the literature. Lun is one of the sensitive geometrical parameter considered to differ from 1 nm to 5 nm in a SEU radiating environment. The effect of Gate-Source/Drain underlap (Lun) on soft error performance in 30 nm Junctionless Transistor (JLT) based on 6T-SRAM cell has been examined through extensive mixed mode-device and circuit simulations using TCAD. The critical dose observed in JLT based 6T-SRAM with Lun ranging from 1 nm to 5 nm to flip the cell is given by Linear Energy Transfer (LET) between 0.05 to 0.06 pC/μm. The simulation result analyzes electrical and SEU radiation parameters to study its impact on JLT based 6T-SRAM cell.

Fulltext

TELKOMNIKA (Telecommunication Computing Electronics and Control)

Effect of Underlap and its Soft Error Performance in 30 nm Junctionless-based 6T-SRAM Cell

This paper puts forward two class E power amplifier implementations in 30 nm DG-SOI FINFET technology. The first configuration using a single transistor has a PAE of 92% that provides a power gain of 37.017 dB. The second configuration is a cascode class E amplifier that has a PAE of 85.16% by giving a power gain of 20.86 dB. The cascode amplifier circuit configuration has been used in order to reduce the voltage stress and thus increases the reliability of RF communication systems. Both the circuits operate at 10 GHz frequency range, by providing an output power of 26 dBm. m. For the single device and cascode configuration, 0.5 mA and 2 mA is the threshold current amplitude above which SEU impact is observed. © Research India Publications.

World University root node

International Journal of Applied Engineering Research

Radiation induced SEU impact on DG-SOI FINFET based class E RF power amplifier

A 2D analytical model for transconductance, Sub-threshold current and Sub-threshold swing for Triple Material Surrounding Gate MOSFET (TMSG) is presented in this paper. Based on the solution of two dimensional Poisson equation, the physics based model of sub-threshold current of the device is derived. The model also includes the effect of gate oxide thickness and silicon thickness on the sub-threshold swing characteristics. Transconductance to drain current ratio of the triple material surrounding gate is calculated since it is a better criterion to access the performance of the device. The effectiveness of TMSG design was scrutinized by comparing with other triple material and dual material gate structures. Moreover the effect of technology parameter variations is also studied and proposed. This proposed model offers basic guidance for design of TMSG MOSFETs. The results of the analytical model are compared with the MEDICI simulation results thus providing validity of the proposed model. © 2013 Elsevier Ltd.

Microelectronics Journal

A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs

The effect of Gate-Source/Drain underlap (L un) on soft error performance in 30 nm common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) have been examined through extensive mixed mode-device and circuit simulations using Sentaurus TCAD. Four different 6T-SRAM topologies, one simultaneously driven double gate-FinFET and three independently driven double gate-FinFETs-based topologies namely Flex-V TH, Flex-PG, and PG-SN are chosen to study the geometrical parameter L un and also to calculate their soft error performance. When L un increases, current decreases due to increase in parasitic series resistance. The simulation results reveal that L un increase in independently driven double gate-FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the L un increase inside the cell, in the inverters, degrade the performance significantly. © 2013 Springer Science+Business Media New York.

Journal of Computational Electronics

Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates

Common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) based 6T-SRAM cells are studied in this paper for their Single Event Upset (SEU) or soft error performance using 3D TCAD simulations. Four different topologies, one common double gate-FinFET-based topology and three independent double gate-FinFET-based topologies namely, Flex-V TH, Flex-PG, and PG-SN are studied to find out their minimum radiation dose required to flip SRAM cell. The simulation results reveal that the independent double gate FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the independent gate devices inside the cell, in the inverters, degrades the performance significantly. © 2012 Elsevier Ltd.