Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

This paper deals with the design of various LC oscillators around 25 GHz which can be used for millimeter wave CMOS radios. Cross coupling is a standard technique used in oscillators and the losses in an LC tank is replenished by the negative resistance of the cross coupled circuit. This paper utilizes cross coupling technique to design oscillators centred around 25 GHz. Four topologies of oscillators are designed in 90nm CMOS technology with a peak to peak output swing of 800mV from a 1.2V supply. The design uses a non ideal inductor modeled with parasitic elements. The simulated phase noise results with the non ideal inductor is around - 97 dBc / Hz at an offset of 1 MHz and the total power consumption is around 60 μW. © 2019 IEEE.

World University root node

Department of Automotive Engineering

School of Mechanical Engineering

Vellore Campus

School of Electronics Engineering

2019 International Conference on Communication and Signal Processing (ICCSP)

Design of Millimeter Wave LC Oscillators for 5G Applications

Department of Control and Automation

School of Electrical Engineering

VIT Unitversity

2019 Innovations in Power and Advanced Computing Technologies (i-PACT)

Automation of Agricultural Tasks with Robotics- Agrobot

2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)

All Time Medicine and Health Device

Presently, comparators have become indispensible in the design of Analog to Digital Converter (ADC) blocks. This work focuses on analyzing, comparing the different works reported on dynamic comparator design from conventional to contemporary needs. This work also advocates the best comparators suitable for different applications based on different parameters. The circuit design with appropriate mathematical design for different comparators was carried out in detail highlighting their pros and cons. Simulation of the reviewed circuits was carried out using gpdk 90nm technology in Cadence environment. The proposed design shows better efficiency as it's delay has been improved by at least 55% as compared to the other designs. © 2019 IEEE.

2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN)

A Review On Dynamic Comparator Topologies

Modular arithmetic based processors are widely used in digital signal processing, image processing, cryptography, etc. All major crypto-systems require the use of modular multipliers in one or more stages of computation. Considerable amount of work has been done to optimize the modular multiplication algorithm and improve the implementation to meet various constraints and requirements. Implementation of a radix-4 based interleaved modular multiplier over 256-bit is provided in this paper. Further, the existing algorithm has been modified and proposed a new algorithm with hardware circuit and both implementation done using Xilinx Virtex-7 (XC7VX485T-FFG1761-2) FPGA. The proposed 256-bit modular multiplication meets around 1 μs of computation time at 122.6 MHz and area is 858 slices. © 2019 IEEE.

Radix-4 Interleaved Modular Multiplication for Cryptographic Applications

Structural Analysis of Low Power and Leakage Power Reduction of Different Types of SRAM Cell Topologies

In this paper, the impact of the substrate on the performance of three channels Stacked Nanosheet Field Effect Transistor (SNSH-FET) is studied, and the Super-Steep-Retrograde silicon substrate (SSR-Si substrate) is presented as a better option for optimum operation. The SSR-Si substrate is achieved by placing 10 nm thick lightly doped SSR-buffer layer on heavily doped Punch-Through-Stopper (PTS) Si substrate. As SNSH-FET is considered as a promising candidate at 7 nm and beyond technology, it is essential to study the performance assessment and perspectives for future analog/RF applications. The analog/RF figure-of-merits (FOMs) such as current-cutoff frequency (f T ), maximum oscillation frequency (f max ), intrinsic gain (A V0 ), gate and drain transconductances (g m and g ds ) along with DC metrics are studied and quantified for different nanosheet width (NSH_W) and thickness (NSH_TH) of intrinsic SNSH-FET. The performance of SNSH-FET has large sensitivity towards NSH_TH variations, around 20% reduction in AV 0 is observed for 2 nm increase in NSH_TH (for NSH_W &gt;30 nm). Finally optimized SNSH-FET structure for 7 nm technology node is presented with Gate-Pitch (GP) and Contacted-Poly-Pitch (CPP) of 48 and 44 nm respectively. Drain-Induced-Barrier-Lowering (DIBL) and Subthreshold Swing (SS) of presented SNSH-FET are 22.8 mV V −1 and 71 mV/dec respectively. © 2019 Elsevier Ltd

Materials Science in Semiconductor Processing

Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut-off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability. © 2018 John Wiley & Sons, Ltd.

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Vedic Mathematics is an ancient Indian mathematics which has unique technique for arithmetic computation. An ASIC based discrete integrator is designed in this paper. This is a novel architecture employs less numbers of multipliers when compared with the conventional one. The architecture could be used in 16-bit ALU. This research used cadence ncsim, rc compiler tool and 90nm technology for synthesis. This paper reveals the study of Vedic multiplier for 16, 32 &amp; 64 bits which is totally unconventional method than shift add. A single architecture also can be used for squaring, cubing as well as Reimann Integral Theorem up to order 4. © BEIESP.

International Journal of Innovative Technology and Exploring Engineering

Asic implementation of high speed discrete integrator using vedic mathematics

In this work, we have discussed a new approach in designing the phase-locked loop (PLL), the proposed circuit is designed with the GDI cell-based PFD, charge pump and low pass filter. For frequency matching and for larger locking state, the design used as D flipflop from the TSMC library. It is used as frequency synthesizers and divides the incoming frequency by 2.This design uses 5 stage current starved voltage control oscillator (CS-VCO). The designed PFD is free from the dead zone issue and it is suitable for the low power applications. the designed PLL works for an average frequency range of 8 GHz and its offset frequency is targeted at 1GHz.This PLL model has low phase noise of -112 dBc/Hz at 1 Mhz frequency which is quite standard and the power consumption of the circuit is 8 Î¼W. The entire work is simulated using Cadence Virtuoso 45 nm Technology. Â© BEIESP.