Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

&nbsp;

&nbsp;

VIT University

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Fulltext

IET circuit devices and systems

A low power and soft error resilience guard-gated Quatro based flip flop in 45nm CMOS technology

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature. © 2019 by the authors. Licensee MDPI, Basel, Switzerland.

Journal of Low Power Electronics and Applications

Design and analysis of SEU hardened latch for low power and high speed applications

CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 μA. © 2018 The Science and Information (SAI) Organization Limited.

International Journal of Advanced Computer Science and Applications

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

In today scenario driver assistance systems such as adaptive cruise control play an important role not only in avoiding accidents but also regulating traffic. The traditional Adaptive cruise control (ACC) system have been added vehicle to vehicle (V2V) communication which enables to transfer speed, acceleration, sensor which plays a key role in the Cooperative adaptive cruise control. The ACC system compared to the CACC system lacks string stability, which is an important factor for smooth transition between states. This paper describes the key features of the ACC system with the advantages of the CACC system. Also we have analyzed the modern predictive control of the ACC system which is an important factor for fuel saving. © IAEME Publication.

World University root node

Department of Embedded Technology

Department of Smart Computing

School of Information Technology and Engineering

International Journal of Mechanical Engineering and Technology

Adaptive cruise control and cooperative cruise control in real life traffic situation

VIT Unitversity

Soft Computing Systems Communications in Computer and Information Science

A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module

Due to the technology scaling the critical charge stored in active nodes is reducing very drastically, so even very small amount of radiation charge could able to disturb the values stored in the active node. In this paper, we have proposed soft-error tolerant flip flop design. The proposed flip-flop utilizes a cross-coupled inverter on the critical path in the master-stage and generates the required differential signals to facilitate the usage of the Quarto soft-error tolerant cell in the slave-stage. We have also designed the DICE cell and compared the area of both DICE (Dual Interlocked Storage Cell) and Quatro latch. The area required for the quarto latch is lesser than that of DICE cell. Total area decreased in the quarto latch is about 25% that of the DICE latch. The proposed design required only 18 transistors to build the DFF, which is very less as compared to the TSPC (True Single Phase Clocking) DFF and conventional DFF which require 25 and 44 transistors respectively. We have implemented a SEU (Single Event Upset) free 4 bit Johnson counter using the proposed DFF. © 2017 IEEE.

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology

2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT)

Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS

Bus protocol plays a vital role in System on chip(SOC) design. SOC’s is a co-ordinatnation of various intellectual property(IP) blocks,communications are handled by utilizing the proprietary/Non proprietary protocol like AXI and OCP. In this paper we are going to deal how two different protocols(AXI and OCP) are connected with the help of bridge by the name AXI-OCP bridge. Different test cases scenario is developed in order to detect functional failures. Our methodology robustness and effectiveness is demonstrated from the obtained results by the improvement of code coverage from the 82% to 91%.Which shows the improvement of 9%. As a result this bus protocol/SOC interconnects guarantee proper communication in between the IP cores in a SOC. © 2016,International Journal of Pharmacy and Technology. All rights reserved.

International Journal of Pharmacy and Technology

Verification of master-slave using AMBA AXI-OCP protocol

A modern real-time embedded system must support multiple concurrently running applications. Double Data Rate Synchronous DRAM (DDR SDRAM) became mainstream choice in designing memories due to its burst access, speed and pipeline features. Synchronous dynamic access memory is designed to support DDR transferring. To achieve the correctness of different applications and system work as to be intended, the memory controller must be configured with pipelined design for multiple operations without delay. The main function of DDR SDRAM is to double the bandwidth of the memory by transferring data (either read operation or write operation) twice per cycle on both the falling and raising edges of the clock signal. The designed DDR Controller generates the control signals as synchronous command interface between the DRAM Memory and other modules. The DDR SDRAM controller supports data width of 64 bits and Burst Length of 4 and CAS (Column Address Strobe) latency of 2 and in this pipelined SRAM controller design, improvement of 28.57% is achieved in performance of memory accessing. The architecture is designed in Modelsim AlTERA STARTER EDITION 6.5b and Cadence (RTL complier and encounter). © Research India Publications.

International Journal of Applied Engineering Research

ASIC implementation of high speed pipelined DDR SDRAM controller design

Modern real-time embedded system must support multiple concurrently running applications. Double Data Rate Synchronous DRAM (DDR SDRAM) became mainstream choice in designing memories due to its burst access, speed and pipeline features. Synchronous dynamic access memory is designed to support DDR transferring. To achieve the correctness of different applications and system work as to be intended, the memory controller must be configured with pipelined design for multiple operations without delay. The main function of DDR SDRAM is to double the bandwidth of the memory by transferring data (either read operation or write operation) twice per cycle on both the falling and raising edges of the clock signal. The designed DDR Controller generates the control signals as synchronous command interface between the DRAM Memory and other modules. The DDR SDRAM controller supports data width of 64 bits and Burst Length of 4 and CAS (Column Address Strobe) latency of 2 and in this pipelined SRAM controller design, improvement of 28.57% is achieved in performance of memory accessing. The architecture is designed in Modelsim AlTERA STARTER EDITION 6.5b and Cadence (RTL complier and encounter). © 2014 IEEE.

International Conference on Information Communication and Embedded Systems (ICICES2014)

ASIC implementation of high speed pipelined DDR SDRAM controller

CMOS Scaling technologies are the main caused for great impact on Analog design. The most severe affect is the reduction in the voltage supply. A double balanced down conversion oscillator mixer using 90 nm CMOS technology is proposed in this work. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The proposed stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires low supply voltage. The DC power consumed by the oscillator is 1.7 mW and mixer is 0.2 mW. The power consumed by discrete structures is high when compared to the proposed stacked structure. At 4.2 GHz a voltage gain of 39 dB and an IIP3 is -12.4 dBm are measured at a supply voltage of 0.9V and with a power consumption of only 1.9 mW. © 2006-2014 Asian Research Publishing Network (ARPN).

ARPN Journal of Engineering and Applied Sciences

A low-power double balanced oscillator mixer design in 90nm CMOS technology

The conventional A current feedback driver with double zeros compensation is proposed for medium to large AMOLED displays. The zeros for lead compensation are implemented with switched-capacitor circuits to reduce chip area. The selection rules for compensation Capacitors and zero capacitors are described to obtain wide bandwidth and high speed. The proposed driver has a settling time of 7us for the panel load of 10k/100pF. This work uses high gain and low gain differential amplifiers to provide constant current through pixel and also make sure that voltage induced in capacitor will keep transistor in saturation to make further operation in emission period. Capacitors used for this feedback loop will provide high speed and high bandwidth. Two phases of operation is done to make current through pixel is constant. The feedback system can be analyzed to check performance by parameters like gain margin and phase margin. This current feedback system gain margin and phase margin can be calculated by keeping Data current initially zero and testing output using test voltage. OTRA, high slew rate TRA are used to improve GM, PM with current feedback. In this paper all feedback techniques are compared by checking their performances based on gain margin and phase margin. © 2006-2014 Asian Research Publishing Network (ARPN).