Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Department of Micro and Nanoelectronics

Underwater wireless communication (UWC) means the transmission of data using wireless channels through the underwater, i.e. radio frequency waves (RF), acoustic waves and optical waves in an unguided water environment. In this review article we focus on underwater optical wireless communications (UWOCs) using optical waves as transmission medium. UWOCs have a much higher communication frequency and therefore a much higher data rate compared to RF and acoustic counter-parts. Due to this high-speed data transfer advantage, UWOC has been very attractive over the past few years. Many applications have been proposed in UWOC systems for protection of the environment, underwater exploration, emergency alerts and military operations etc. However, underwater channels also suffer from extreme absorption and dispersion. In recent years, a variety of innovative methods of network architecture have been developed to meet these technological challenges, which are different from standard terrestrial, open space optical communications. In this article we give a detailed overview of various research activities on UWOC. © 2020 IEEE.

World University root node

School of Electronics Engineering

Vellore Campus

2020 7th International Conference on Smart Structures and Systems, ICSSS 2020

Underwater wireless optical communication systems: A survey

We present a performance enhancement evaluation of n + doped graded InGaN drain/source region-based HfO2/InAlN/AlN/GaN/AlN on SiC metal-oxide-semiconductor high electron mobility transistor (MOS-HEMTs) with a T-shaped gate. Impact on the device characteristics with the inclusion of a HfO2 surface passivation layer and an AlN buffer layer in the MOS-HEMT structure as a performance booster has been analyzed for the HEMT device with 30 nm gate length using Silvaco ATLAS TCAD. The proposed MOS-HEMT exhibits an outstanding performance, with an enhanced power gain cut-off frequency (fmax) of 366 GHz, a current gain cut-off frequency (ft) of 426 GHz, and a off-state breakdown voltage (Vbr) of 81 V. The high-k (high permittivity) HfO2 based metal oxide semiconductor HEMT device experiences a low off-state gate leakage current (Ig ~ 10−11A/mm) and a high Ion/Ioff ratio of 109. The InAlN/GaN/AlN heterostructures demonstrate improved two-dimensional electron gas (2DEG ~ 5.3 × 1013 cm−2), carrier mobility (μ) of 1256 Cm2/V-s and drain current density of (Ids) 2.7 A/mm. A large signal analysis performed at 30 GHz yielded a maximum of 28% power-added efficiency. The high JFoM of 34.506 THz V (Johnson Figure of Merit = ft × Vbr) and (ft.fmax)1/2 of 394.86 GHz indicate the potential applicability of the HfO2/InAlN/GaN MOS-HEMTs in high-frequency and high-power applications. © 2020 The Authors

Fulltext

Journal of Science: Advanced Materials and Devices

Performance analysis of HfO2/InAlN/AlN/GaN HEMT with AlN buffer layer for high power microwave applications

Junctionless inserted oxide FinFET (JL-iFinFET) is presented, its performance metrics are quantified and compared with JL-FinFET and JL-Stacked-Nanowire-FET (JL-SNWFET) respectively for the same foot-print on the wafer. The Random-Dopant-Fluctuation (RDF) and Metal-Gate-Granularity (MGG) are major variability sources in nano-transistors. Impedance Field Method is used to analyze the statistical variability performance of all three structures caused by RDF and MGG. The result shows JL-SNWFET provides superior DC figure-of-merits and 40% less statistical variability than JL-FinFET with a 10% increase in delay and considerable increase in fabrication complexity. The JL-iFinFET offers 30% lesser process-induced threshold voltage and on-current variations compare to JL-FinFET, without deteriorating delay and RF metrics due to its superior electrostatic control over the channel and multi-channel configuration. Fabrication of JL-iFinFET is also possible without adding much complexity in FinFET process it can be a major contender for continued scaling with JL-Transistors (JLTs). © 2019 Elsevier GmbH

VIT Unitversity

AEU - International Journal of Electronics and Communications

Improved statistical variability and delay performance with junctionless inserted oxide FinFET

Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are realized by segregating the partial products into two segments. The most significant bit (MSB) segment is accumulated as per Dadda tree structure and the least significant bit (LSB) segment is accumulated by approximate technique. The proposed Imprecise Multipliers, namely IM1 and IM2, are realized using Verilog HDL and simulated using TSMC 65nm process. For sake of comparison, the proposed multipliers IM1 and IM2 are compared with existing approximate multipliers. From the reported results, it may be noted that IM1 performs better in terms of area-delay product, power-delay product. While IM2 achieves a higher peak signal-To-noise ratio (PSNR) among all the multipliers existing in the literature. © 2021 World Scientific Publishing Company.

Journal of Circuits, Systems and Computers

Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications

Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45 μm in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294 μs. The simulation results are carried using Specter. © World Scientific Publishing Company

Design of artificial neuron network with synapse utilizing hybrid CMOS transistors with memristor for low power applications

In this work, a novel Minimum Variance Distortion less Response (MVDR) beamformer architecture in which the adaptive weight vector is computed based on modified Column wise Givens Rotation (CGR) is presented. As compared to the conventional MVDR beamformer, Quadrature Rotation Decomposition (QRD)-MVDR is suitable for hardware realizations. To improve the real-time performance requirements of the MVDR Beamformer, a parallel pipe-lined CGR based QRD architecture is employed in the adaptive weight computation stage of the MVDR Beamformer. A computationally efficient MVDR beamforming algorithm, which requires to compute only the R matrix in QRD, rather than matrix inverse is used to develop the architecture. The developed architecture generates the adaptive weight vector in 3.9ns, and hence a beam can be formed in 0.25msec time. The designed architecture is implemented using Verilog Register Transfer Level (RTL) coding, and the functional equivalence checking was carried with the Verasonics Vantage-64 Ultrasound Research Platform (URP). The architecture is also ported on Xilinx Kintex-7 FPGA based Emulation set up and validated in real-time, targeting medical ultrasound imaging applications. The developed architecture is compared with the existing architecture implementations. It concludes that the architecture is superior in terms of computational time and can be adapted for ultrafast adaptive beamforming applications. © 2013 IEEE.

IEEE Access

Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging

In this paper, the performance of a N+- CdTe/ n- Hg0.824675Cd0.175325Te/ p+- Hg0.824675Cd0.175325Te n–i–p photodetector with a heavily doped CdTe material as a window for terahertz frequency application has been analyzed. The detector is designed and studied in respect of electrical and optical characteristics. The results obtained with the help of TCAD tool are compared with the results obtained on the basis of the analytical model. The proposed photodetector is suitable for operation at a wavelength of 30 μm at liquid nitrogen temperature (77 K). It has the characteristics of dark current of 4.6×10-9A, quantum efficiency (η) ~ 73.93%, responsivity (R) ~ 17.9 A/W, specific detectivity (D∗) ~ 1.44×109mHz1/2W-1, noise equivalent power (NEP) ~ 0.3×10-16W. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.

Optical and Quantum Electronics

Performance analysis of N+-CdTe/n0-Hg0.824675Cd0.175325Te/p+-Hg0.824675Cd0.175325Ten-i-p photodetector operating at 30 μm wavelength for terahertz applications

In this paper, a variable-size power-efficient two-parallel prime factor MDC FFT architecture is proposed which uses a novel reconfigurable processing element pair (RPEP). The prior reconfigurable FFT approaches merely concentrate on FFT architectures with a wide range of FFT sizes. The processing elements/stages are connected to or disconnected from the architecture to vary the size of the FFT. As a result, the hardware is underutilized when the processing elements are disconnected (unused). In the proposed approach, power reduction and effective utilization of hardware are concentrated rather than increasing the number of FFT sizes. The proposed RPEP structure contains two two-parallel processing element which can be either connected in serial or parallel. If one of the processing elements in the RPEP must be disconnected to reduce the FFT size, then the two two-parallel processing elements in the RPEP are configured as a single four-parallel processing element. Due to parallel processing, the frequency of operation is reduced by half and dynamic power is also reduced significantly. The architecture is designed in UMC 65 nm technology and can be configured in seventeen sizes ranging from 8 to 2048-points. The design occupies 0.67 mm.sq and consumption 17.74 mW power when operated at 100 MHz. © 2020 Elsevier GmbH

A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications

We present a new 600 V breakdown optimized vertical GaN Split-Gate Trench power MOSFET (SGTMOSFET) device with significantly reduced specific on-resistance and lower reverse capacitance. Using TCAD numerical simulations, we demonstrate that the SGTMOSFET exhibits about 30% lower specific on-resistance and about five times reduction in the reverse capacitance when compared to a conventional TG-MOSFET with similar breakdown voltage. © 2020 IEEE.

2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, WiPDA Asia 2020

Optimization of Vertical GaN SGT-MOSFET for Low Ron

Carbon Nanotube Field Effect Transistor (CNTFET) is cutting-edge technology where the demand for transistor scaling is increasing day by day industrially. Beyond 10 nm scaling of MOSFET is introducing several limitations like short channel effect, drain induced barrier lowering, less Ion/off ratio etc. Instead of modifying the existing MOSFET technologies, recent new technologies are considered as future and as per prediction of the Global Market for carbon nanotubes report, CNTFET is going to make a severe impact in the semiconductor market. In this paper, first AC analysis is done by varying number of channels of GAA-CNTFET of Common Source Amplifier and results are shown in the form of a graph. Then AC analysis is performed by varying diameter of GAACNTFET and from the result of this analysis which maximum gain was obtained is chosen. Similarly, AC analysis is formed by varying oxide thickness (tox) and dielectric material (kox) and from the results of these analyses, the best-case gain is obtained for single stage, two stages, and three stages common source amplifier using CNTFET on 11 nm technology. In the frequency domain, it corresponds to 19.102 dB for single stage, 38.26 dB for two-stages and 56.34 dB for three stages. © 2020 IEEE.