Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

One of the increasingly difficult challenges in testing System-On-a-Chip (SoC) is dealing with the large amount of test vectors that must be stored in the tester and transferred between the testers. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. Hence a test data compression and decompression scheme using reconfigurable multipliers has been presented in this paper. This scheme stores test vectors as a product of two deterministic vector seeds and uses the intermediate states of the multiplication of the vector seeds using the reconfigurable serial multiplier, to realize the test vector. Since multipliers are one of the widely used components in many SOCs, this method reduces significant hardware by exploiting the advantage of using the existing circuitry in the circuit under test for decompression. It provides a twofold advantage by reducing the amount of test data that needs to be stored on the tester and reducing the time for transferring test data from the tester to the circuit-under-test resulting in better encoding efficiency. Linear decompression with free variables is used. The encoding efficiency could be further explored with high percent of free variables. This scheme works best for circuits within built multipliers and significant reduction in hardware is observed. Experimental results obtained with ISCAS'89 benchmark shows the efficiency of this scheme on reduction of test data volume as well as the test time.

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

World University root node

International Journal of Engineering and Technology

System-on-a-chip test data compression and decompression with reconfigurable serial multiplier

This paper proposes a single precision floating point low power multiplier that conforms to the IEEE 754 standard. The 24×24 significand multiplication is achieved by using four parallel 12×12 bit multipliers, each of these are implemented using Radix-4 modified Booth algorithm using array type architecture. Switching activity is reduced in the proposed multiplier by using the idea of data wordlength reduction and by reducing the spurious switching in the adder block of the multiplier. Data wordlength reduction technique of truncation is used effectively to reduce the power consuming transitions. Further reduction in switching (spurious and computation) is achieved by synchronizing the inputs in a predetermined chronological sequence to the adders in the adder block by making use of latches and delay circuits. The whole floating point multiplier unit is mapped to TSMC 0.18μm CMOS process. Power savings is improved for this floating point multiplier, although the use of latches increases the hardware penalty. Power, delay and PDP (power delay product) of proposed data truncation is compared with existing floating point multipliers schemes. Savings in PDP of the proposed data truncation is ~64.67% and ~46.12% compared to existing IEEE compliant multiplier architecture and truncation scheme. © Research India Publications.

International Journal of Applied Engineering Research

Design of low power floating point multiplier with reduced switching activity in deep submicron technology

The performance of the multiplier is of high importance in any Digital Signal Processor (DSPs). Apart from the speed its precision is also plays a vital role. This is rectified by using Floating Point numbers in these multipliers. But it may consume more silicon area and power. In this paper we propose a method for fast floating point multiplication based on Dadda Algorithm. The coding is done for 32-bit single precision floating point multiplication using Verilog and synthesized using Xilinx ISE v13.4. Further the results are compared with the previous work. These results clearly indicate that our method using Dadda method can have a great impacton improving the speed and reduce the area and power consumed by the Digital Signal Processors. © Research India Publications.

Design of floating point multiplier for signal processing applications

This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used. © 2013 IEEE.

VIT Unitversity

2013 International Conference on Computer Communication and Informatics

Adaptive test clock scheme for low transition LFSR and external scan based testing

Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at the filter taps effectively uses the computation re-use concept. Experimental results on a 10-tap programmable FIR filter show that the proposed multiplier scheme can provide a power reduction of 39.7% and significant improvements in the performance compared to conventional floating-point carry save array multiplier implementations.

Department of Instrumentation

School of Electrical Engineering

Low power floating point computation sharing multiplier for signal processing applications

In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.

2012 International Symposium on Electronic System Design (ISED)

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the pattern. After filling the X-bits for shift power reduction, the patterns are compressed based on shifted alternating frequency directed run-length coding, which is suitable for encoding pre-computed test set of embedded cores in System-on-Chip(SoC). The experimental results on ISCAS'89 benchmark circuits show that our scheme provides better compression efficiency as well as significant reduction in test power.

2012 International Conference on Advances in Computing and Communications

Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies

Reduction of testing power with pulsed scan flip-flop for scan based testing

In any general purpose processor the use of conventional full precision multipliers results in increase in the power, area and computational time. So, multipliers being the basic key element of any computation unit take its own importance in decreasing the power as well as increase in the speed. Twin Precision Multipliers has flexible and reconfigurable computational units are creating a trend which overcomes the drawback of the conventional full precision multipliers and also resulting in higher computational throughput of the processors. This paper proposes low power reconfigurable multiplier architecture based reordering of partial products, which reduces the power consumption based on partial products reordering. Reordering of partial products technique is applied on both High Performance Multiplication (HPM) and Dadda column reduction techniques to obtain low power reconfigurable twin precision multiplier.

Low power reconfigurable multiplier with reordering of partial products

This paper proposes a novel approach for reducing the shifting and capture power by a fan-out aware modified adjacent X-filling technique. This approach reduces the time complexity and number of iterations in addition to the reduction of test power. Experimental results obtained from ISCAS'89 circuits are compared with existing techniques prove that the proposed ATPG methodology is suitable to test the scan based system-on-chip architecture with reduced testing power.