Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Diabetic retinopathy is a common condition of an ailment where the retina is harmed on the grounds that fluid breaks away from the walls of blood vessels into the retina. The large population is affected by diabetic retinopathy and hence research in the area of automated screening has acquired major research interest in the scientific community. The diagnosing features for diabetic retinopathy comprises of identifying deformations of minute blood vessel in form of exudates and its features occurring in and around the regions of fundus which will result into exudes, hemorrhages, or microaneurysms. This feature is often hard to be classified by naked eyes and need trained personnel for close inspection before making diagnosis. Therefore, a comprehensive machine learning tool is in the demand for automated diabetic retinopathy detection. Neural networks have given promising results in the field of classification. Therefore, we present a hybrid neural network-based method with realistic clinical potential. In this study, we present a neuro-fuzzy technique, which is developed for identification of exudates in retinal images and is utilized for the extraction of essential features from the retinal images of patient’s eyeballs. We trained this hybrid neural network base technique over a set of 25,600 training images for color retinal images and tested it over 12,000 testing image set for binocular model. The method achieves an accuracy of 95.4% recognition on non-noisy images and 93% on noisy images; thereby giving a consistency rate of 91% in correspondence with the ophthalmologist.

VIT Unitversity

Department of Information Security

School of Computer Science and Engineering

Vellore Campus

Electronics

School of Electronics Engineering

Chennai Campus

The International Journal of Electrical Engineering & Education

Detection of exudates using neuro-fuzzy technique

Layout is an important step towards Integrated Circuit(IC) designing. The following research work focuses on the techniques that can be applied on layout to optimise the digital IC. The work discusses about other methods as well that are proposed to optimise ICs. However, this research work shows a step-by-step approach in implementing Euler’s Path and Minimum Distance Rule. It targets the change in the switching power, layout area and delay in the circuit to show the effect of the proposed methods. Euler’s Path and Minimum Distance Rule are the two techniques that are used on an example circuitry that implements (AB+CD)' Boolean expression. Cadence Virtuoso simulation tool is used for simulations and quantitatively analyse the mentioned parameters. Post layout simulations are used to get more realistic results because it takes parasitic elements into account as well. The results from layouts with and without the above techniques applied, is compared, showing a decrease in switching power, delay and layout area for the circuit with the optimization techniques. The results in this work show that with improvement in layouts of digital ICs, we can make ICs more reliable. More complex circuitry will benefit from these techniques because they will need lesser layout area which will aid in adding more circuitry and increasing the complexity further more. © BEIESP.

World University root node

International Journal of Innovative Technology and Exploring Engineering

Layout optimization using Euler’s path and minimum distance rule

The finite impulse response (FIR) filter are class of digital filter are extensively used in signal processing and in communication system applications such as noise reduction, echo cancellation and image enhancement etc. Designing a FIR filter with less computation time, low power and by using minimum hardware playing a major role in overall performance of the application where FIR filter is involved. The research work presented in this paper has been carried out to fulfil the above said aim. In this research work, 16 tap FIR filter has been implemented using newly proposed floating point Computation Sharing High Speed Multiplier (CSHM). Since in FIR filter, floating point multiplication is involved in each and every tap of filter operation, bringing the floating point multiplication architecture with less computation time, low power and with minimum hardware will automatically improve the performance of FIR filter. The newly proposed computation sharing multiplier differs from existing computation sharing multiplier with respect to fixed alphabet entries in a precomputer unit and efficient computation of distributed arithmetic based vector scalar product. Front end and backend design of a 16 tap FIR filter using newly proposed CSHM and existing CSHM has been carried out using Cadence® nclaunch®, RC® and Encounter® tool with tsmc 180 nm technology library. Comparison result of 16 tap FIR filter shows that 18% reduction in chip power, 13% reduction in chip area and 26% reduction in cell count has been achieved with newly proposed floating point CSHM compare to 16 tap FIR filter designed with existing CHSM. This research work also proposes efficient automation algorithms which improve the design for manufacturability (DFM) of a post layout of a 16 tap FIR filter designed which will improve the reliability of integrated circuits. There are many DFM guidelines have to be followed during layout design. In this research work, the automation algorithm has been proposed for one of the DFM guideline called VIA-Redundancy. The aim of this automation algorithm is to replacing single VIA with double VIA wherever possible. In case of “L” transition routing, single contacts can be very sensitive to resistivity spread and defect. The probability to have too resistive transition will be very much minimized by inserting a new contact which reduces electro-migration effect. Through this automation algorithm redundancy percentage of all the VIA’s of FIR filter designed has been increased without compromising chip area, power and computation time much. The specialty of this automated algorithm is that this can be used to any design which has been implemented on the same platform and technology node. The proposed algorithm automated through Tcl 8.6, UNIX platform. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.

Cluster Computing

Reliability improved, high performance FIR filter design using new computation sharing multiplier: suitable for signal processing applications

Many Integrated Circuits (or ICs) consisting of sequential logic use a clock signal for synchronizing different components of the circuit. The clock tree distributes the clock signals from its source to all the components and hence, any uncertainty in the arrival times of the clock signals can intensely limit the performance of the whole circuit. Generating the clock tree network with minimum skew and power consumption plays a vital role in digital IC design. On this research work, the three methods i) low swing ii) buffer upsizing and iii) polarity assignment techniques has been used together to achieve minimum power and skew in a clock tree network. It has been observed that applying polarity assignment technique after the low swing and buffer upsizing techniques reduces the clock tree network delay to 25% and power consumption of the clock tree network lies between first two techniques and hence this method gives counterbalanced clock tree network with respect to skew and power consumption. The research work has been carried out using tsmc 180nm technology library, Cadence® Virtuoso®, Cadence® Layout editor and Cadence® Assura® tools. © 2006-2018 Asian Research Publishing Network (ARPN).

ARPN Journal of Engineering and Applied Sciences

A counterbalancing technique for skew and power management of clock tree

In this paper, an 8-bit asynchronous wave-pipelined arithmetic logic unit has been modified with set of 8 arithmetic and 12 logical operations. All the internal modules have been modified in order to reduce power and latency by using ASIC semi-custom design flow in cadence® environment using gpdk-180-nm technology. This modified design has achieved reduction in power by 45%, reduction in delay by 19%, reduction in area by 43%, reduction in cell count by 49% as compared to the existing ALU. © 2018, Springer Nature Singapore Pte Ltd.

Lecture Notes in Electrical Engineering

8-Bit Asynchronous Wave-Pipelined Arithmetic Logic Unit

Background: Memories occupy the majority of chip area, and the response time for any system depends on its memory too. So, SRAMs are critical to the speed of processor operations and thus need to be rigorously optimized. The optimizations have to be in such a way that the constraints of better performance as well as reliability are met. Methods/Statistical analysis: The proposed bit cell is compared with conventional 6T bit cell for access time, read stability, on-current,and off-current, and the suitable sense amplifiers and decoder are analyzed. Findings: The proposed architecture for SRAM design meets the criteria of faster access time and read stability as compared to the conventional 6T SRAM. Write 1 operation achieves a rise of 16%, while write 0 and read 1 are better than 6T by 70 and 90%, respectively. The design was implemented on 28 nm FD-SOI platform. Application/Improvements: The proposed design has the better read stability as compared to the conventional 6T SRAM bit cell design. © 2018, Springer Nature Singapore Pte Ltd.

28 nm FD-SOI SRAM Design Using Read Stable Bit Cell Architecture

This paper presents the design of Wishbone compliant memory controller which behaves as interface between processor and memory. Memory controller is a digital circuit which manages the flow of data to and fro from the processor to the memory. Instead of processor handling all the read and write operations into the memory, it allocates its work to memory controller so that processor can do some other work during the same time. This in turn leads to increase processor’s performance. The memory controller used in this work supports synchronous static random access memory (SSRAM), synchronous dynamic random access memory (SDRAM), and synchronous chip select device. It also deals with the verification and functional coverage of the controller. The design part has been done using Xilinx ISE tool, and the verification part has been done using Mentor Graphics Questa Sim 10.0b. © 2018, Springer Nature Singapore Pte Ltd.

Design and Verification of Memory Controller with Host Wishbone Interface

In this research work, low power and low area based multiplier architecture is proposed for high speed applications. There are a few enhancement made to the conventional shift and add multiplier architecture, the normal adder for addition has been replaced by the Error Tolerant[ET] concept for designing the adder and activating the adder cells by current multiplication bit of the multiplier constant. In the normal design, carry propagation dissipates the significant amount of dynamic power consumption. In contrast to the existing architectures, in this proposed architecture the multiplexer is removed and when the multiplicand has a zero as a bit the adder is bypassed. Shifting the partial products and multiplier bits is done by using the down counter. The proposed ET shift and add multiplier is synthesized in the XILINX software and simulated in ModelSim. The result for 8x8 multiplier shows the proposed design reduces the power consumption and delay by 55mw and 49ns respectively compared to the existing one. The area, power, and delay optimization is achieved by using the error tolerant shift and add multiplier. Hence making it suitable for image processing application because minimum amount error is tolerable. © IAEME Publication.

International Journal of Mechanical Engineering and Technology

A design of low power and low area multiplier using shift and add architecture

Floating point multiplication is one of the most frequently used arithmetic operation, but the high memory requirement and speed requirement of the IEEE-754 standard floating point multiplier prohibits its implementation in many systems which requires fast computing. Hence floating point multiplication becomes one of the main research areas. This research work aims for developing a new floating point architecture which reduces computation time, area and the power consumption when compared to many existing floating point multiplier. After the extensive literature survey, the new architecture has been identified which took Computation Sharing High speed Multiplier [CSHM] and Karatsuba algorithm as base architecture’s. This new architecture may reduce the area, power and increase speed further compared to existing CSHM based multipliers by replacing normal multiplication of alphabet set of precomputers unit of CSHM into multiplication of Karatsuba algorithm. The new developed architecture will be having the advantage of both CSHM as well as karatsuba algorithm. The semi custom flow of above proposed architecture will be carried out in cadence® in 180nm technology. © 2018, Institute of Advanced Scientific Research, Inc.. All rights reserved.

Journal of Advanced Research in Dynamical and Control Systems

A review on floating point multiplier architecture using semi custom vlsi design flow

Design of an integrated circuit layout is said to be the characterization of the components and elements of the integrated circuit in 3-dimension in geometrical models which represents the silicon layers, oxide layers, metal and polysilicon. Optimizing the layout helps in producing less parasitic effects, interconnect delays, power dissipation and signal integrity in an IC. The proposed work reduces total layout area of the application by incorporating following methods together: 1) depletion sharing, 2) minimum distance rule and 3) different metal layers. The proposed technique is practiced on 40 transistor D-flip flop[1] layout using Cadence® virtuoso® 64 tool. On using the minimum distance rule method along with depletion sharing the total layout area is reduced by 71.60% and on combining all the three methods area reduces by 73.44% with reference to schematic driven layout of example circuitry. In proposed layout, in order to subdue the reliability issue, single vias are replaced with double vias wherever possible. Simulation after post layout is done and the corresponding power calculation has been identified for the layout of the example circuitry and results clearly say that total layout area reduction is reducing the power consumption directly in total. © 2017 Institute of Biotechnology and Genetic Engineering. All Right Reserved.

Pakistan Journal of Biotechnology

Full custom layout optimization techniques

As the complexity of electronic systems increasing day by day, power consumption has emerged one of the main design constraints. In recent years, there has been increasing demand for high speed low power consumption electronic systems. Flip flops are critical timing elements in any electronic system. Here power consumption is reduced by reducing dynamic power consumption. In this paper, I proposed dual edge triggered flip flop for low power systems which will work as normal dual edge triggered flip flop. Reduction in the number of transistors along with double edge triggering technique helps to reduce power dissipation. Because of the property of dual edge triggering, circuit speed is doubled compared to single edge triggered flip flop. © Research India Publications.

International Journal of Applied Engineering Research

Dual edge triggered flip flop for low power systems

High performance multiplier designs are the prime need of emerging digital filtering operations. This research study presents a novel architecture of reduced area computation sharing multiplier for Finite Impulse Response (FIR) filter. The same architecture is extended for the floating point applications. The chosen pre-computer alphabet set is the most prominent feature of this architecture. The proposed integer based Computation Sharing High speed Multiplier (CSHM) efficiently computes the vector scalar product based on the distributed arithmetic. The proposed CSHM (8*8) shows 29.81% of area and 46% of power optimization over existing CSHM style. The experimental results for Look up Table (LUT) based implementation shows 57% improvement than the LUT required to implement a existing 8*8 CSHM based FIR filter. The proposed design style is also extended for Floating Point (FP) multiplication. The 4 tap Floating Point Finite Impulse Response (FP FIR) filter is designed in Xilinx environment (No. of LUT's 5919) and TSMC 180 nm technology (power 29.5 mW and area 212636.79 um2) using proposed CSHM. The performance results get improves in terms of power and area over conventional design style. © Maxwell Scientific Organization, 2015.

Fulltext

Research Journal of Applied Sciences, Engineering and Technology

A Novel Less Area Computation Sharing High Speed Multiplier Architecture for FIR Filter Design

Background: Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition to this, number of new techniques are used in order to reduce significantly latency, area and for implementation on FPGA compared to existing implementations. Findings: Parallel architecture is used for generating partial products using radix-10 recoding technique for signed-digit of a BCD multiplier having set of digits between the range [-5, 5] and a positive set of multiplicand multiples coded in XS-3. Use of this encoding has various advantages like, as XS-3 is a self-complementing code, finding a negative of it is by just complementing the bits of respective number. Also the redundancy in XS-3 code is utilized for generating multiplicand multiples in a simple, faster and a carry-free way. Implemented design has three stages. Partial product generation, reduction and final conversion to BCD. For to implement the design in hardware the partial product reduction architecture is modified here to use a bank of ripple carry adder trees. ODDS representation uses 4-bit binary encoding technique which is similar to non-redundant BCD code, for this reason conventional VLSI circuit techniques such as carry-save adders and compression trees can be used effectively to perform operations on decimal numbers. Conclusion: To show the advantages of the resulted design, RTL model for 8 × 8-digit and 16 × 16-digits multiplication has been synthesized and implemented in Virtex-5 FPGA device. Results shows that the multiplier is about 10-15% delay efficient with existing work and about 14-18% area efficient.

Indian Journal of Science and Technology

Implementation of Fast Radix-10 BCD Multiplier in FPGA

Background/Objectives: As the size of the chip reduces, nanoscale devices have become more susceptible to manufacturing faults, interference from radiations and transient faults. Many of these errors are not permanent but it causes malfunctioning of circuit either due to the complexity of the circuit or due to the interaction with the software. In this paper, an area and power efficient BIST with self repairing technique has been proposed, which detect and repair the faults in the circuit. Methods/Statistical Analysis: In this research work, a novel Built-In Self-Test (BIST) architecture with self repairing circuit is proposed. The novelty of this architecture is that testing is done along with the self repairing. The Self repairing circuit repairs the fault in the circuit during testing phase itself which increases the reliability of the circuit. Since the insertion of test pattern externally, BIST architecture does not alter the basic multiplier structure. Findings: Average power dissipation of the proposed Built-in self test and self repairing of array multiplier architecture is reduced by 36% since the use of a power efficient test pattern generator. Self repairing has been accomplished by the use of hardware redundancy technique. Also a TMR based self repairing architecture for real time self repairing has been proposed and its area and power dissipation is compared with the other self repairing architecture. Result shows that the BIST with repairing technique is good for low power applications while the TMR based self repairing method is good for real time self repairing applications. The proposed technique can be extended to self repairing processor.

Built-In Self Test and Self-Repairing Circuit for Array Multipliers

Objectives: Finite Impulse Response (FIR) filters are widely used in image and signal processing applications and responsible for more total power dissipation. This research work presents modified Distributed Arithmetic (DA)-based approach for realization of low power FIR digital filter. Methods/Statistical Analysis: Power reduction in modified DA-based filter is achieved by turning offthe MOS components whenever the input samples of circuit are zero. The proposed filter reduces power consumption by disabling adder operation when inputs are zero. In the conventional DSP applications, it is observed that the average of the zero input sample is very high. Therefore, substantial reduction in power consumption can be obtained by proposed modified DA-based architecture. The proposed DA-based FIR filter is designed using Xilinx® ISE design tool and Cadence® EDA tool. Findings: The proposed work proved that the power reduction is achieved in modified DA-based FIR filter realization when compared with existing LUT-less DA-based architecture of FIR filter. Simulation results shows that proposed architecture can achieve significant power reduction with fewer percentage increases in area and delay for different architectures. For four tap FIR filter 12.5% power reduction is achieved, at the cost of 0.63% extra chip area and 1% increased delay in comparison with conventional DA-based filter architecture. Therefore, the proposed filter can achieve even greater power saving for higher order FIR filters and for more number of zeros in the inputs sample. The proposed technique can also be used for reconfigurable architectures where filter coefficients change during runtime. Conclusion: A low power modified DA-based FIR digital Filter is proposed. Power reduction in proposed design is due to turning offMOS components and is linearly related to number of zeros in input and order of the filter.