Sakthivel R
Associate Professor Grade 2
Publications - 55Publications - 55
Publications - 55Publications (55)
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Journal ArticleLow Leakage Power Vedic Multiplier using Standard Cell Design2015 | Indian Society for Education and Environment
Journal ArticleLow Power Modulo 2n+1 Multiplier Using Data Aware Adder Tree2015 | Elsevier BV
Open Access- ArticlesDesign and implementation of double tail dynamic comparator for low power 3-bit flash ADC2015 | Research India Publications
- ArticlesDesign of modified explicit pulse data-close-to-output flip-flop2015 | Asian Research Publishing Network
Journal ArticleEnergy Efficient Low Area Error Tolerant Adder with Higher Accuracy2014 | Springer Science and Business Media LLC- Journal ArticleLow power high throughput reconfigurable stream cipher hardware VLSI architectures2014 | Inderscience Publishers
Proceedings ArticleDesign of high quality factor fully-differential CMOS current conveyor for a complex filter application2013 | IEEE- Journal ArticleDesign of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver2013 | Institute of Electronics, Information and Communications Engineers (IEICE)Open Access
- Book ChapterLow-Power Area Efficient Reconfigurable Pipelined Two’s Complement Multiplier with Reduced Error2012 | Springer Berlin Heidelberg
Proceedings ArticleLow power energy efficient pipelined multiply-accumulate architecture2012 | ACM Press- Proceedings ArticleAn optimized architecture to perform image compression and encryption simultaneously using modified DCT algorithm2011 | IEEE
- ArticlesPhase-locked loop with high stability against process variation and gain-boosting charge pump for current matching characteristics2010 | EuroJournals, Inc.
