Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

The scalability and complexity nature of the integrated circuit design makes the verification process more complicated and time-consuming. Therefore, in the present modern-day SOC’s there is a strong need for verification architectures with increased reusability and easy accessibility. The UVM methodology-based verification architecture with reusable components is one of the widely accepted test bench architectures for carrying out such functional verification. This paper presents a UVM methodology based functional verification of the SPI protocol core with a dedicated architecture. First the SPI core is modeled using Verilog RTL. Then using the reusable components in UVM + System Verilog environment, the SPI core is verified under two modes such as i) SPI communication with wishbone interface and ii) SPI Master-Slave communication. © 2021 Institute of Physics Publishing. All rights reserved.

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Electronics

School of Electronics Engineering

Chennai Campus

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Journal of Physics: Conference Series

UVM methodology based functional verification of SPI protocol

This research work presents the application-specific integrated circuit (ASIC) implementation of one dimensional (1 × 8) and two dimensional (8 × 8) discrete cosine transform using the reversible logic gates. During the DCT implementation, the integer DCT method of realization is adopted, thereby eliminating the occurrence of floating-point operations in the data path architecture. Thus, the integer mode of DCT realization using reversible logic gates in the proposed DCT architecture improves the delay, power and area of the 1D and 2D DCT data path structure when compared with the normal real DCT implementation. The proposed methodology of DCT implementation includes the construction of full adder and full subtractor using reversible gates and then extended for the realization of the DCT butterfly structure. Especially in this research method, Peres reversible gate is used for the implementation of full-adder and Thapliyal Ranganathan (TR) gate for the implementation of full subtractor, respectively. Thus, the 1D and 2D DCT implementation using reversible logic gates in 180nm technology nodes consume an overall area of 55504.311 sq.µm and 1122324.044 sq.µm respectively. © 2021 Institute of Physics Publishing. All rights reserved.

Implementation of two-dimensional (2D) discrete cosine transform (DCT) using reversible gates

This work presents a computation efficient image watermarking very large-scale integration (VLSI) architecture with improved robustness and throughput. The computational complexity is reduced by the incorporation of integer DCT, whereas the throughput is improved by the implementation of a four-stage pipeline architecture. Further, in the present work, the secret watermark bits are inserted in the DCT low-frequency coefficients using a mean adaptive threshold value, which not only results in a minimum degradation to the host image quality but also increases the robustness of the proposed algorithm. The VLSI implementation of the proposed algorithm using CadenceⓇ circuit design tools in 180 nm technology demonstrates an overall power consumption of 4.47 mW and a throughput of 2.5 Gbps that are better than the results reported in the literature. © 2020 Elsevier Ltd

Computers and Electrical Engineering

Computation-efficient image watermarking architecture with improved performance

In this paper, a generic rgb to gray scale converter intellectual property (IP) core is implemented and verified. First verification environment for the device under test (DUT) is implemented using system verilog class libraries and Qsys tool of Quartus software. Then the device under test (DUT) is verified by performing two tests. First test is video file reader test which is carried out to check the functionality of the device under test and another test is constrained random test which is performed to verify the device under test outputs with randomly generated expected outputs. Both the test are performed using Modelsim software. © BEIESP.

International Journal of Innovative Technology and Exploring Engineering

Implementation and verification of rgb to grayscale converter ip using system verilog

Digital image watermarking has become more popular due to its applications in copyright protection and secret communication. Most of the image watermarking algorithms reported till date involve modification of the host contents for embedding a secret data, leading to a reduced robustness and a limited embedding capacity. In the present work, a novel spatial domain watermarking scheme called Pixel Value Search Algorithm (PVSA) is proposed using a linear search operation to achieve high robustness and a theoretically unlimited embedding capacity. In the proposed scheme, secret data are embedded into a host image by mapping their intensity values into row and column locations. Due to this linear mapping of secret data, the host structural content is not altered. In addition, multiple watermarks can be mapped into a single host image using the PVSA technique. The proposed algorithm is verified using MATLAB® simulations and its performance characteristics are assessed using a standard benchmark tool called strimark. Experimental results illustrate the robustness of the PVSA technique against the attacks of Gaussian blurring, Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, mean and median filtering, histogram equalization, image sharpening, intensity transformation, unsharp filtering, JPEG attack, etc. Subsequently an ASIC implementation of the PVSA algorithm is carried out using Verilog HDL and various modules of the Cadence® EDA tool so as to integrate the chip as a watermark co-processor. The ASIC implementation using a 0.18 μm technology at an operating frequency of 100 MHz consumes a power of 326.34 μW for the complete hardware architecture. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.

Multimedia Tools and Applications

An ASIC based invisible watermarking of grayscale images using pixel value search algorithm (PVSA)

Background: The rapid advancement of multimedia technology has made the data communication and data sharing so comfortable through wireless network and Internet. During this multimedia communication, the piracy of the multimedia content is a primary concern (i.e. anyone can duplicate or alter the originality). One of the most efficient techniques to protect the multimedia data is watermarking. It is the process of adding a secret digital signature to the host content in a visible or invisible form. The process of watermarking will be of reversible or irreversible nature. Method: In this paper, a reversible watermarking strategy using prediction technique with its hardware architecture is proposed. In the VLSI implementation aspect three different architectural structures are proposed as pipelined, parallel and dataflow architecture with embedding concept. Findings: Finally, all the three architectural designs are modelled and implemented using Verilog HDL. The entire process is integrated in a specific chip. Application: It can be used as a separate co-processor for carrying out the watermarking in real time with any multimedia devices. © Springer Nature Singapore Pte Ltd. 2018.

VIT Unitversity

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Pipelined and Parallel Architecture of Reversible Watermarking for Greyscale Images

Objective: In this paper, the design and verification of AMBA AXI3 protocol are carried out in a coverage mode analysis using Verilog HDL language. Method: The design of AXI protocol is made according to its architecture specifications, and its functionality is verified using QuestaSim tool. In the AXI protocol analysis, the burst-based transactions, i.e. writing and reading of increment burst have been implemented. Findings: In addition to that the AMBA AXI efficiency is evaluated by calculating performance metrics bus utilization, busy count and valid count. In the entire paper, a verification environment is created for the verification of AXI protocol as a verification IP for modern SOC architectures. Applications: High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation. © Springer Nature Singapore Pte Ltd. 2018.

Design and Verification of AMBA AXI3 Protocol

In this paper, 2D integer wavelet transform based watermarking is carried out for the grayscale image with its VLSI architectural implementations. In the 2D integer wavelet transformation the lifting scheme is adopted and the watermarking operation is carried out in the LL2 frequency subbands. The entire watermark embedding process and extraction process are modeled in MATLAB and analyzed against the signal processing attacks like compression, salt & pepper noise, rotation and Intensity transformation attacks. Finally the same algorithm is modeled using Verilog HDL and implemented using ALTERA QUARTUS-II. © 2016 IEEE.

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

Real time watermarking of grayscale images using integer DWT transform

Data hiding in one of the easiest technique to authenticate and resolve the copyright issues of multimedia data. This paper proposes a new VLSI architecture for data hiding in grayscale images using neighbour mean image interpolation technique, as this mechanism will have a minimum computation complexity. In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity. © 2015 IEEE.

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

FPGA implementation of data hididng in grayscale imagesusing neighbour mean interpolation

Watermarking the digital data is a familiar technique to authenticate and resolve the copyright issues of multimedia data. This paper proposes a new VLSI architecture for watermarking grayscale images using weighted median prediction operation, as this mechanism will have a minimum computation complexity. In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity. © 2015 IEEE.

A VLSI architecture for watermarking of grayscale images using weighted median prediction

This paper deals with the VLSI Architecture of Integer wavelet based on lifting scheme. Firstly the problems faced by conventional transforms and the differences between conventional and wavelet transform is presented. Later the mechanisms of DWT, IWT based on lifting schemes is presented. Then a new efficient VLSI architectures for forward, backward, integrated IWT based on lifting are explained. From the simulation results we can observe that the designed architecture is more efficient in terms of area required for the design. © Research India Publications.

International Journal of Applied Engineering Research

VLSI architecture for lifting scheme based Integer wavelet transform

This paper mainly focuses on verifying the important features of advanced extensible interface (AXI). Verifying the memory transactions of AXI includes the verification of all the five channels write address, write data, write response, read address and read data. In this work a Verification Intellectual Property cores (VIP) based methodology is used to carry out the verification Process. In the VIP design the entire test environment is modeled using system verilog and the read, write transactions from the same and different memory locations has been verified with the quantitative values of Busy Count, Valid Count and its Bus Utilization. Verifying the System connectivity during write and read cycles is also one of the fundamental features verified in this paper. © 2015 IEEE.

Department of Chemical Engineering

School of Chemical Engineering

Vellore Campus

2015 International Conference on Communications and Signal Processing (ICCSP)

Verification of memory transactions in AXI protocol using system verilog approach

Verification is the process of exploring the correct functioning of the design. It is not possible to guarantee a design without proper verification, because misunderstanding and misinterpretation of the specifications, incorrect interaction between the cores and IPS leads to unexpected behavior of the system. Functional verification plays a key role in validating a design and its Functionality. AXI2OCP Bridge connects two different protocols i.e. advanced extensible interface and open core protocol. AXI2OCP Bridge helps in converting AXI 3.0 format signals to OCP format signals, AXI address to OCP address and AXI data to OCP data. Protocols With effective Bus utilization leads to have a faster data rate with increased performance. Measuring the Bus utilization parameter for the AXI 3.0 protocols generated test cases and functional verification of the AXI2OCP Bridge using system verilog language is the main idea of this paper. © 2015 IEEE.

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

Functional verification of the Axi2OCP bridge using system verilog and effective bus utilization calculation for AMBA AXI 3.0 protocol

This paper proposes a new spatial domain watermarking of grayscale images and has also shown its VLSI Implementation without altering its content in real time using a secret key. The secret key is generated by searching the watermark pixel values in host image content and the location maps are marked in secret key. Therefore this algorithm is called PVSA- Pixel Value Search Algorithm. The proposed algorithm does not make any change in the host image. Thus it shows high robustness to signal processing attacks. The watermark extraction process is simple as the host content is extracted based on key. We have evaluated the robustness of the algorithm against several signal processing attacks using MATLAB. Finally we have implemented the same algorithm in verilog HDL using Altera Quartus-II. © 2015 IEEE.

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

A real time watermarking of grayscale images without altering it's content

Background: In this digital era, the authentication and proof of ownership has become a vital part in all the multimedia data content like audio, image and video. Data Hiding is one of the familiar methodologies used to authenticate and resolve the issues of copyrights of the digital data. Methods: In this paper the FPGA (Field Programmable Gate Array) implementation of Data Hiding using reversible Dual Image concept is carried out on a gray scale image. Here the FPGA implementation is carried out with and without the concept of pipelining. Findings: In the data hiding process the secret key is embedded in the host image content and analyzed with the values of PSNR (Peak Signal to Noise Ratio) and Embedding capacity. In the last, a comparison for the pipelined and non pipelined mode of data hiding process has been done for the values of area, power and timing. From the results it is noted that the pipelined mode of data hiding gives better result in terms of very less embedding time compared to non pipelined mode with a lesser power consumption. As this data hiding methodology involves only simple operation it is easy to implement as FPGA chip using Verilog HDL Modelling language. Here the entire data hiding operation is carried out by the hardware chip, not by software running on hardware, hence the process of data hiding is fast when compared with all other software implementations. As the whole process of embedding is taking place in real time, we can embed this FPGA data hiding chip as a separate co-processor the data hiding operation with any multimedia device.

Indian Journal of Science and Technology

A FPGA Implementation of Dual Images based Reversible Data Hiding Technique using LSB Matching with Pipelining

Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This will significantly reduces the power dissipation. Various TSPICE simulation with different input sequences is done. The design has been simulated using Tanner 13.0 EDA tool with 0.25 μm technology. © 2013 IEEE.